remove source2

chipsalliance · Aug 5, 2024 · b7d4b7a · b7d4b7a
1 parent 68e1dda
commit b7d4b7a
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Showing 3 changed files with 20 additions and 13 deletions.
diff --git a/t1/src/LaneZvbb.scala b/t1/src/LaneZvbb.scala
@@ -29,7 +29,6 @@ class LaneZvbbRequest(datapathWidth: Int) extends VFUPipeBundle {
 
 class LaneZvbbResponse(datapathWidth: Int)  extends VFUPipeBundle {
   val data = UInt(datapathWidth.W)
-  val source2 = UInt(datapathWidth.W)
 }
 
 @instantiable
@@ -114,20 +113,27 @@ class LaneZvbb(val parameter: LaneZvbbParam)
     zvbbROR32,
   ))
 
-  val zvbbSLL64_32 = (0.U((parameter.datapathWidth).W) ## zvbbSrc).asUInt << zvbbRs(5, 0)
-  val zvbbSLL64_16 = ((0.U(16.W) ## zvbbSrc16a).asUInt << zvbbRs16a(4, 0)).asUInt(31, 0) ##
-                     ((0.U(16.W) ## zvbbSrc16b).asUInt << zvbbRs16b(4, 0)).asUInt(31, 0)
-  val zvbbSLL64_8 = ((0.U(8.W) ## zvbbSrc8a).asUInt << zvbbRs8a(3, 0)).asUInt(15, 0) ##
-                    ((0.U(8.W) ## zvbbSrc8b).asUInt << zvbbRs8b(3, 0)).asUInt(15, 0) ##
-                    ((0.U(8.W) ## zvbbSrc8c).asUInt << zvbbRs8c(3, 0)).asUInt(15, 0) ##
-                    ((0.U(8.W) ## zvbbSrc8d).asUInt << zvbbRs8d(3, 0)).asUInt(15, 0)
+  // val zvbbSLL64_32 = ((0.U((parameter.datapathWidth).W) ## zvbbSrc).asUInt << zvbbRs(5, 0)).asUInt(63, 0)
+  // val zvbbSLL64_16 = ((0.U(16.W) ## zvbbSrc16a).asUInt << zvbbRs16a(4, 0)).asUInt(31, 0) ##
+  //                    ((0.U(16.W) ## zvbbSrc16b).asUInt << zvbbRs16b(4, 0)).asUInt(31, 0)
+  // val zvbbSLL64_8 = ((0.U(8.W) ## zvbbSrc8a).asUInt << zvbbRs8a(3, 0)).asUInt(15, 0) ##
+  //                   ((0.U(8.W) ## zvbbSrc8b).asUInt << zvbbRs8b(3, 0)).asUInt(15, 0) ##
+  //                   ((0.U(8.W) ## zvbbSrc8c).asUInt << zvbbRs8c(3, 0)).asUInt(15, 0) ##
+  //                   ((0.U(8.W) ## zvbbSrc8d).asUInt << zvbbRs8d(3, 0)).asUInt(15, 0)
+  val zvbbSLL64_32 = ((0.U((parameter.datapathWidth).W) ## zvbbSrc).asUInt << zvbbRs(5, 0)).asUInt(31, 0)
+  val zvbbSLL64_16 = ((0.U(16.W) ## zvbbSrc16a).asUInt << zvbbRs16a(4, 0)).asUInt(15, 0) ##
+                     ((0.U(16.W) ## zvbbSrc16b).asUInt << zvbbRs16b(4, 0)).asUInt(15, 0)
+  val zvbbSLL64_8 = ((0.U(8.W) ## zvbbSrc8a).asUInt << zvbbRs8a(3, 0)).asUInt(7, 0) ##
+                    ((0.U(8.W) ## zvbbSrc8b).asUInt << zvbbRs8b(3, 0)).asUInt(7, 0) ##
+                    ((0.U(8.W) ## zvbbSrc8c).asUInt << zvbbRs8c(3, 0)).asUInt(7, 0) ##
+                    ((0.U(8.W) ## zvbbSrc8d).asUInt << zvbbRs8d(3, 0)).asUInt(7, 0)
   val zvbbSLL64 = Mux1H(vSew, Seq(
     zvbbSLL64_8,
     zvbbSLL64_16,
     zvbbSLL64_32,
   ))
   val zvbbSLL = zvbbSLL64(parameter.datapathWidth-1, 0)
-  val zvbbSLLMSB = zvbbSLL64(2*parameter.datapathWidth-1, parameter.datapathWidth)
+  // val zvbbSLLMSB = zvbbSLL64(2*parameter.datapathWidth-1, parameter.datapathWidth)
 
   val zvbbANDN = zvbbSrc & (~zvbbRs)
 
@@ -141,8 +147,6 @@ class LaneZvbb(val parameter: LaneZvbbParam)
       zvbbROR,
       zvbbSLL,
       zvbbANDN,
-    )
-  )
-  response.source2 := Mux(request.opcode === 7.U, zvbbSLLMSB, 0.U)
+  ))
 }
 
diff --git a/t1/src/decoder/attribute/isSwrite.scala b/t1/src/decoder/attribute/isSwrite.scala
@@ -210,6 +210,10 @@ object isSwrite {
       "vzext.vf2",
       "vzext.vf4",
       "vzext.vf8",
+      // rv_zvbb
+      "vwsll.vv",
+      "vwsll.vx",
+      "vwsll.vi",
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }

diff --git a/t1/src/decoder/attribute/isVtype.scala b/t1/src/decoder/attribute/isVtype.scala
@@ -186,7 +186,6 @@ object isVtype {
       "vrol.vv",
       "vror.vv",
       "vwsll.vv",
-      "vwsll.vv",
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }