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[ci] update t1 test case cycle data
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github-actions authored and Avimitin committed Nov 19, 2024
1 parent b1b43c5 commit aee7d3d
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Showing 4 changed files with 53 additions and 53 deletions.
6 changes: 3 additions & 3 deletions .github/designs/blastoise/t1emu.json
Original file line number Diff line number Diff line change
Expand Up @@ -13,11 +13,11 @@
"intrinsic.softmax": 7032,
"rvv_bench.ascii_to_utf16": 11282,
"rvv_bench.ascii_to_utf32": 4694,
"rvv_bench.byteswap": 19955,
"rvv_bench.byteswap": 20052,
"rvv_bench.mandelbrot": 247231,
"rvv_bench.memcpy": 34534,
"rvv_bench.memcpy": 34718,
"rvv_bench.memset": 11501,
"rvv_bench.mergelines": 24911,
"rvv_bench.strlen": 22697,
"rvv_bench.utf8_count": 151124
"rvv_bench.utf8_count": 151134
}
62 changes: 31 additions & 31 deletions .github/designs/blastoise/t1rocketemu.json
Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
{
"asm.memcpy": 751,
"asm.mmm": 51749,
"asm.smoke": 8001,
"asm.strlen": 7986,
"asm.utf8_count": 205,
"asm.memcpy": 774,
"asm.mmm": 51794,
"asm.smoke": 8051,
"asm.strlen": 8009,
"asm.utf8_count": 232,
"codegen.vaadd_vv": 170452,
"codegen.vaadd_vx": 490423,
"codegen.vaaddu_vv": 170452,
Expand Down Expand Up @@ -499,30 +499,30 @@
"codegen.vxor_vx": 123814,
"codegen.vzext_vf2": 13454,
"codegen.vzext_vf4": 4260,
"intrinsic.conv2d_less_m2": 2498,
"intrinsic.linear_normalization": 3350,
"intrinsic.matmul": 61748,
"intrinsic.softmax": 6793,
"mlir.axpy_masked": 4048,
"mlir.conv": 125859,
"mlir.hello": 131,
"mlir.matmul": 56059,
"mlir.maxvl_tail_setvl_front": 700,
"mlir.rvv_vp_intrinsic_add": 469,
"mlir.rvv_vp_intrinsic_add_scalable": 807,
"mlir.stripmining": 8882,
"mlir.vectoradd": 15530,
"pytorch.demo": 31521,
"pytorch.matmul": 69793,
"rvv_bench.ascii_to_utf16": 677090,
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"rvv_bench.byteswap": 399524,
"rvv_bench.chacha20": 39957,
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"rvv_bench.mergelines": 564228,
"rvv_bench.poly1305": 39957,
"rvv_bench.strlen": 219139,
"rvv_bench.utf8_count": 2283382
"intrinsic.conv2d_less_m2": 2550,
"intrinsic.linear_normalization": 3373,
"intrinsic.matmul": 61798,
"intrinsic.softmax": 6822,
"mlir.axpy_masked": 4098,
"mlir.conv": 125881,
"mlir.hello": 175,
"mlir.matmul": 56109,
"mlir.maxvl_tail_setvl_front": 749,
"mlir.rvv_vp_intrinsic_add": 520,
"mlir.rvv_vp_intrinsic_add_scalable": 858,
"mlir.stripmining": 8931,
"mlir.vectoradd": 15575,
"pytorch.demo": 31524,
"pytorch.matmul": 69835,
"rvv_bench.ascii_to_utf16": 690528,
"rvv_bench.ascii_to_utf32": 230907,
"rvv_bench.byteswap": 399659,
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"rvv_bench.mandelbrot": 529131,
"rvv_bench.memcpy": 672015,
"rvv_bench.memset": 290646,
"rvv_bench.mergelines": 561502,
"rvv_bench.poly1305": 40010,
"rvv_bench.strlen": 218969,
"rvv_bench.utf8_count": 2230705
}
4 changes: 2 additions & 2 deletions .github/designs/rookidee/t1emu.json
Original file line number Diff line number Diff line change
Expand Up @@ -8,8 +8,8 @@
"mlir.stripmining": 27810,
"rvv_bench.ascii_to_utf16": 16070,
"rvv_bench.ascii_to_utf32": 6057,
"rvv_bench.byteswap": 43275,
"rvv_bench.memcpy": 46320,
"rvv_bench.byteswap": 43098,
"rvv_bench.memcpy": 46538,
"rvv_bench.memset": 19350,
"rvv_bench.mergelines": 38578,
"rvv_bench.strlen": 34517,
Expand Down
34 changes: 17 additions & 17 deletions .github/designs/rookidee/t1rocketemu.json
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
{
"asm.mmm": 51749,
"asm.smoke": 4564,
"asm.mmm": 51794,
"asm.smoke": 4614,
"codegen.vaadd_vv": 118067,
"codegen.vaadd_vx": 354504,
"codegen.vaaddu_vv": 118067,
Expand Down Expand Up @@ -430,19 +430,19 @@
"codegen.vxor_vx": 88767,
"codegen.vzext_vf2": 11223,
"codegen.vzext_vf4": 3241,
"intrinsic.conv2d_less_m2": 2498,
"mlir.hello": 130,
"mlir.rvv_vp_intrinsic_add": 442,
"mlir.rvv_vp_intrinsic_add_scalable": 640,
"mlir.stripmining": 27798,
"rvv_bench.ascii_to_utf16": 676092,
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"rvv_bench.chacha20": 39957,
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"rvv_bench.utf8_count": 2350031
"intrinsic.conv2d_less_m2": 2550,
"mlir.hello": 175,
"mlir.rvv_vp_intrinsic_add": 493,
"mlir.rvv_vp_intrinsic_add_scalable": 691,
"mlir.stripmining": 27847,
"rvv_bench.ascii_to_utf16": 689602,
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"rvv_bench.chacha20": 40010,
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}

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