[cases] loop after signaling sim finish

chipsalliance · Oct 20, 2024 · a41fb69 · a41fb69
1 parent 7295b05
commit a41fb69
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/tests/t1_main.S b/tests/t1_main.S
@@ -13,5 +13,6 @@ _start:
     li x1, 0x40000000
     li x2, 0xdeadbeef
     sw x2, 0(x1)
+    j .
 
     .p2align 2