[ci] update test case cycle data

chipsalliance · Jul 29, 2024 · 9ca203b · 9ca203b
1 parent 1cd70a0
commit 9ca203b
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Showing 3 changed files with 17 additions and 17 deletions.
diff --git a/.github/cases/blastoise/default.json b/.github/cases/blastoise/default.json
@@ -273,9 +273,9 @@
   "codegen.vse16_v": 4013,
   "codegen.vse32_v": 3403,
   "codegen.vse8_v": 4623,
-  "codegen.vsetivli": 469,
-  "codegen.vsetvl": 469,
-  "codegen.vsetvli": 469,
+  "codegen.vsetivli": 468,
+  "codegen.vsetvl": 468,
+  "codegen.vsetvli": 468,
   "codegen.vsext_vf2": 23212,
   "codegen.vsext_vf4": 4241,
   "codegen.vslide1down_vx": 866515,
@@ -502,12 +502,12 @@
   "rvv_bench.ascii_to_utf16": 1583717,
   "rvv_bench.ascii_to_utf32": 704008,
   "rvv_bench.byteswap": 3353190,
-  "rvv_bench.chacha20": 2,
+  "rvv_bench.chacha20": 3,
   "rvv_bench.mandelbrot": 4056017,
   "rvv_bench.memcpy": 2131958,
   "rvv_bench.memset": 438601,
   "rvv_bench.mergelines": 3337924,
-  "rvv_bench.poly1305": 2,
+  "rvv_bench.poly1305": 3,
   "rvv_bench.strlen": 877595,
   "rvv_bench.utf8_count": 6340810
 }
diff --git a/.github/cases/machamp/default.json b/.github/cases/machamp/default.json
@@ -1,6 +1,6 @@
 {
   "mlir.rvv_vp_intrinsic_add": 422,
-  "mlir.rvv_vp_intrinsic_add_scalable": 575,
+  "mlir.rvv_vp_intrinsic_add_scalable": 576,
   "mlir.hello": 113,
   "mlir.stripmining": 13447,
   "asm.mmm": 91467,
@@ -271,9 +271,9 @@
   "codegen.vse16_v": 3981,
   "codegen.vse32_v": 3371,
   "codegen.vse8_v": 4591,
-  "codegen.vsetivli": 437,
-  "codegen.vsetvl": 437,
-  "codegen.vsetvli": 437,
+  "codegen.vsetivli": 436,
+  "codegen.vsetvl": 436,
+  "codegen.vsetvli": 436,
   "codegen.vsext_vf2": 39423,
   "codegen.vsext_vf4": 6444,
   "codegen.vslide1down_vx": 1631043,
@@ -438,11 +438,11 @@
   "rvv_bench.ascii_to_utf16": 1460100,
   "rvv_bench.ascii_to_utf32": 631209,
   "rvv_bench.byteswap": 3259012,
-  "rvv_bench.chacha20": 2,
+  "rvv_bench.chacha20": 3,
   "rvv_bench.memcpy": 1875735,
   "rvv_bench.memset": 244343,
   "rvv_bench.mergelines": 3137781,
-  "rvv_bench.poly1305": 2,
+  "rvv_bench.poly1305": 3,
   "rvv_bench.strlen": 710445,
   "rvv_bench.utf8_count": 5729743
 }
diff --git a/.github/cases/sandslash/default.json b/.github/cases/sandslash/default.json
@@ -1,6 +1,6 @@
 {
   "mlir.rvv_vp_intrinsic_add": 428,
-  "mlir.rvv_vp_intrinsic_add_scalable": 648,
+  "mlir.rvv_vp_intrinsic_add_scalable": 649,
   "mlir.hello": 115,
   "mlir.stripmining": 3598,
   "asm.mmm": 91467,
@@ -271,9 +271,9 @@
   "codegen.vse16_v": 5523,
   "codegen.vse32_v": 4817,
   "codegen.vse8_v": 6229,
-  "codegen.vsetivli": 821,
-  "codegen.vsetvl": 821,
-  "codegen.vsetvli": 821,
+  "codegen.vsetivli": 820,
+  "codegen.vsetvl": 820,
+  "codegen.vsetvli": 820,
   "codegen.vsext_vf2": 134897,
   "codegen.vsext_vf4": 19825,
   "codegen.vslide1down_vx": 6151901,
@@ -438,11 +438,11 @@
   "rvv_bench.ascii_to_utf16": 1371573,
   "rvv_bench.ascii_to_utf32": 583341,
   "rvv_bench.byteswap": 3556325,
-  "rvv_bench.chacha20": 2,
+  "rvv_bench.chacha20": 3,
   "rvv_bench.memcpy": 1704891,
   "rvv_bench.memset": 130507,
   "rvv_bench.mergelines": 3038622,
-  "rvv_bench.poly1305": 2,
+  "rvv_bench.poly1305": 3,
   "rvv_bench.strlen": 715296,
   "rvv_bench.utf8_count": 4797754
 }