[tests] fix lsu write probe.

chipsalliance · Oct 17, 2024 · 868b317 · 868b317
1 parent 685dfe0
commit 868b317
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/t1/src/lsu/LSU.scala b/t1/src/lsu/LSU.scala
@@ -283,7 +283,7 @@ class LSU(param: LSUParameter) extends Module {
       probeWire.slots(index).dataMask        := write.io.enq.bits.data.mask
       probeWire.slots(index).dataData        := write.io.enq.bits.data.data
       probeWire.slots(index).dataInstruction := write.io.enq.bits.data.instructionIndex
-      probeWire.slots(index).writeValid      := write.io.enq.valid
+      probeWire.slots(index).writeValid      := write.io.enq.fire
       probeWire.slots(index).targetLane      := OHToUInt(write.io.enq.bits.targetLane)
     }
     probeWire.reqEnq := reqEnq.asUInt