fix vs1 and vs2 error

chipsalliance · Aug 2, 2024 · 7daad5b · 7daad5b
1 parent 79cdfd8
commit 7daad5b
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/t1/src/LaneZvbb.scala b/t1/src/LaneZvbb.scala
@@ -37,8 +37,8 @@ class LaneZvbb(val parameter: LaneZvbbParam)
   val response: LaneZvbbResponse = Wire(new LaneZvbbResponse(parameter.datapathWidth))
   val request : LaneZvbbRequest  = connectIO(response).asTypeOf(parameter.inputBundle)
 
-  val zvbbSrc: UInt = request.src(0) // vs2
-  val zvbbRs: UInt = request.src(1) // vs1 or rs1
+  val zvbbSrc: UInt = request.src(1) // vs1 or rs1
+  val zvbbRs: UInt = request.src(0) // vs2
 
   val zvbbBRev  = VecInit(zvbbSrc(parameter.datapathWidth-1, 0).asBools.reverse).asUInt // element's bit reverse
   val zvbbBRev8 = VecInit(zvbbSrc(parameter.datapathWidth-1, 0).asBools.grouped(8).map(s => VecInit(s.reverse)).toSeq).asUInt // byte's bit reverse