[rtl] fix ffoIndex width.

chipsalliance · Oct 16, 2024 · 69a7240 · 69a7240
1 parent c312572
commit 69a7240
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/t1/src/laneStage/LaneExecutionBridge.scala b/t1/src/laneStage/LaneExecutionBridge.scala
@@ -40,7 +40,7 @@ class LaneExecuteRequest(parameter: LaneParameter, isLastSlot: Boolean) extends
 
 class LaneExecuteResponse(parameter: LaneParameter, isLastSlot: Boolean) extends Bundle {
   val data:           UInt              = UInt(parameter.datapathWidth.W)
-  val ffoIndex:       UInt              = UInt(log2Ceil(parameter.vLen / 8).W)
+  val ffoIndex:       UInt              = UInt(log2Ceil(parameter.vLen / parameter.laneNumber).W)
   val crossWriteData: Option[Vec[UInt]] = Option.when(isLastSlot)(Vec(2, UInt(parameter.datapathWidth.W)))
   val ffoSuccess:     Option[Bool]      = Option.when(isLastSlot)(Bool())
   val fpReduceValid:  Option[Bool]      = Option.when(parameter.fpuEnable && isLastSlot)(Bool())

diff --git a/t1/src/laneStage/LaneStage3.scala b/t1/src/laneStage/LaneStage3.scala
@@ -15,7 +15,7 @@ class LaneStage3Enqueue(parameter: LaneParameter, isLastSlot: Boolean) extends B
   val data:             UInt         = UInt(parameter.datapathWidth.W)
   val pipeData:         UInt         = UInt(parameter.datapathWidth.W)
   val mask:             UInt         = UInt((parameter.datapathWidth / 8).W)
-  val ffoIndex:         UInt         = UInt(log2Ceil(parameter.vLen / 8).W)
+  val ffoIndex:         UInt         = UInt(log2Ceil(parameter.vLen / parameter.laneNumber).W)
   val crossWriteData:   Vec[UInt]    = Vec(2, UInt(parameter.datapathWidth.W))
   val sSendResponse:    Bool         = Bool()
   val ffoSuccess:       Bool         = Bool()