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[nix] add cover flow support
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Signed-off-by: Avimitin <[email protected]>
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Avimitin authored and sequencer committed Oct 7, 2024
1 parent 0631f34 commit 51d96dc
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Showing 4 changed files with 30 additions and 3 deletions.
9 changes: 8 additions & 1 deletion nix/t1/conversion/sv-to-vcs-simulator.nix
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,10 @@ stdenv.mkDerivation rec {
"-timescale=1ns/1ps"
"-file"
"filelist.f"
"-cm"
"line+cond+fsm+tgl+branch+assert"
"-cm_dir"
"./cm"
]
++ lib.optionals (enableTrace) [
"+define+T1_ENABLE_TRACE"
Expand Down Expand Up @@ -65,13 +69,16 @@ stdenv.mkDerivation rec {
mkdir -p $out/bin $out/lib
cp $mainProgram $out/lib
cp -r $mainProgram.daidir $out/lib
cp -r ./cm.vdb $out/lib
# We need to carefully handle string escape here, so don't use makeWrapper
tee $out/bin/$mainProgram <<EOF
#!${bash}/bin/bash
export LD_LIBRARY_PATH="$out/lib/$mainProgram.daidir:\$LD_LIBRARY_PATH"
_argv="\$@"
${vcs-fhs-env}/bin/vcs-fhs-env -c "$out/lib/$mainProgram \$_argv"
cp -r $out/lib/cm.vdb ./cm.vdb
chmod +w -R ./cm.vdb
${vcs-fhs-env}/bin/vcs-fhs-env -c "$out/lib/$mainProgram -cm_dir ./cm.vdb \$_argv"
EOF
chmod +x $out/bin/$mainProgram
Expand Down
4 changes: 4 additions & 0 deletions nix/t1/run/run-vcs-emu.nix
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@ stdenvNoCC.mkDerivation (finalAttr: {
emuDriverArgsArray=(
"+t1_elf_file=${testCase}/bin/${testCase.pname}.elf"
${lib.optionalString emulator.enableTrace "+t1_wave_path=${testCase.pname}.fsdb"}
"-cm assert"
)
emuDriverArgs="''${emuDriverArgsArray[@]}"
emuDriver="${emulator}/bin/${emulator.mainProgram}"
Expand Down Expand Up @@ -78,6 +79,9 @@ stdenvNoCC.mkDerivation (finalAttr: {
mv perf.json $out/
fi
cp -v cm.log "$out"
cp -vr cm.vdb "$out"
${lib.optionalString emulator.enableTrace ''
cp -v ${testCase.pname}.fsdb "$out"
cp -vr ${emulator}/lib/${emulator.mainProgram}.daidir "$out"
Expand Down
12 changes: 11 additions & 1 deletion script/emu/src/Main.scala
Original file line number Diff line number Diff line change
Expand Up @@ -180,7 +180,8 @@ object Main:
s"No cached emulator selection nor --emu argument was provided"
)

val isTrace = finalEmuType.get.endsWith("-trace")
val isTrace = finalEmuType.get.contains("-trace")
val isCover = isTrace

val finalConfig = tryRestoreFromCache("config", config)
if finalConfig.isEmpty then
Expand All @@ -204,6 +205,7 @@ object Main:
s"+t1_elf_file=${caseElfPath}"
)
++ optionals(isTrace, Seq(s"+t1_wave_path=${outputPath / "wave.fsdb"}"))
++ optionals(isCover, Seq(s"-cm assert"))
++ optionals(!leftOverArguments.isEmpty, leftOverArguments)

if dryRun.value then return
Expand Down Expand Up @@ -259,6 +261,14 @@ object Main:

Logger.info("Driver finished")

if isCover then
if os.exists(os.pwd / "cm.vdb") && os.exists(os.pwd / "cm.log") then
os.move(os.pwd / "cm.vdb", outputPath / "cm.vdb", replaceExisting = true)
os.move(os.pwd / "cm.log", outputPath / "cm.log", replaceExisting = true)
Logger.info(s"Coverage database saved under ${outputPath}/cm.vdb")
else
Logger.error("No cm.vdb cm.log found")

if os.exists(os.pwd / "perf.json") then
os.move(os.pwd / "perf.json", outputPath / "perf.json", replaceExisting = true)

Expand Down
8 changes: 7 additions & 1 deletion t1emu/src/TestBench.scala
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,12 @@ import chisel3.util.circt.dpi.{
RawClockedVoidFunctionCall,
RawUnclockedNonVoidFunctionCall
}
import chisel3.util.{HasExtModuleInline, PopCount, UIntToOH, Valid}
import chisel3.util.{BitPat, HasExtModuleInline, PopCount, UIntToOH, Valid}
import chisel3.ltl.{CoverProperty, Sequence}
import org.chipsalliance.amba.axi4.bundle._
import org.chipsalliance.t1.t1emu.dpi._
import org.chipsalliance.t1.rtl.{T1, T1Parameter}
import org.chipsalliance.rvdecoderdb.Instruction

@instantiable
class TestBenchOM extends Class {
Expand Down Expand Up @@ -283,4 +285,8 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
scoreboard.bits := 0.U
}
}
generator.parameter.decoderParam.allInstructions.map { instruction: Instruction =>
val issueMatch = Sequence.BoolSequence(issue.instruction === BitPat("b" + instruction.encoding.toString))
CoverProperty(issueMatch, label = Some(s"t1_cover_issue_${instruction.name}"))
}
}

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