[t1rocket] fix wrong logic when reg wait and write at same clock

chipsalliance · Aug 24, 2024 · 4c6bd79 · 4c6bd79
1 parent 0338833
commit 4c6bd79
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala
@@ -183,7 +183,7 @@ class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTil
     )
   )
 
-  when(rocketProbe.waitWen && !rocketProbe.isVector && rocketProbe.waitWaddr =/= 0.U)( // should this judge vector?
+  when(rocketProbe.waitWen && !rocketProbe.isVector && rocketProbe.waitWaddr =/= 0.U && !rocketProbe.rfWen)(
     printf(
       cf"""{"event":"RegWriteWait","idx":${rocketProbe.waitWaddr},"cycle":${simulationTime}}\n"""
     )