[ipemu] filter 64-bit width instructions in t1 emu coverage flow

chipsalliance · Oct 14, 2024 · 4a8882a · 4a8882a
1 parent 8820af1
commit 4a8882a
Showing 1 changed file with 26 additions and 3 deletions.
diff --git a/t1emu/src/TestBench.scala b/t1emu/src/TestBench.scala
@@ -253,10 +253,10 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
     RegInit(0.U.asTypeOf(Valid(UInt(16.W))))
   }
   vrfWriteScoreboard.foreach(scoreboard => dontTouch(scoreboard))
-  val instructionValid =
+  val instructionValid        =
     (laneProbes.map(laneProbe => laneProbe.instructionValid ## laneProbe.instructionValid) :+
       lsuProbe.lsuInstructionValid :+ t1Probe.instructionValid).reduce(_ | _)
-  val scoreboardEnq    =
+  val scoreboardEnq           =
     Mux(t1Probe.instructionIssue, UIntToOH(t1Probe.issueTag), 0.U((2 * generator.parameter.chainingSize).W))
   vrfWriteScoreboard.zipWithIndex.foreach { case (scoreboard, tag) =>
     val writeEnq: UInt = VecInit(
@@ -285,7 +285,30 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
       scoreboard.bits  := 0.U
     }
   }
-  generator.parameter.decoderParam.allInstructions.map { instruction: Instruction =>
+  // coverage
+  // unsupported 64-bit instructions for 32-bit xlen
+  val unsupportedInstF = Seq(
+    // format: off
+    "vfwadd.vf", "vfwadd.vv", "vfwadd.wf", "vfwadd.wv",
+    "vfwcvt.f.f.v", "vfwcvt.f.x.v", "vfwcvt.f.xu.v", "vfwcvt.rtz.x.f.v", "vfwcvt.rtz.xu.f.v", "vfwcvt.x.f.v", "vfwcvt.xu.f.v",
+    "vfwmacc.vf", "vfwmacc.vv", "vfwmsac.vf", "vfwmsac.vv",
+    "vfwmul.vf", "vfwmul.vv", "vfwnmacc.vf", "vfwnmacc.vv",
+    "vfwnmsac.vf", "vfwnmsac.vv", "vfwredosum.vs", "vfwredusum.vs",
+    "vfwsub.vf", "vfwsub.vv", "vfwsub.wf", "vfwsub.wv", 
+    // format: on
+  )
+  val unsupportedInst = Seq(
+    // format: off
+    "vfncvt.f.f.w", "vfncvt.f.x.w", "vfncvt.f.xu.w", "vfncvt.rod.f.f.w", "vfncvt.rtz.x.f.w", "vfncvt.rtz.xu.f.w", "vfncvt.x.f.w", "vfncvt.xu.f.w",
+    "vfslide1up.vf", "vfslide1down.vf",
+    "vl1re64.v", "vl2re64.v", "vl4re64.v", "vl8re64.v", 
+    "vle64.v", "vle64ff.v", "vloxei64.v", "vlse64.v", "vluxei64.v",
+    "vmfle.vf", "vmfle.vv", "vse64.v", "vsext.vf8", "vsoxei64.v", "vsse64.v", "vsuxei64.v", "vzext.vf8"
+    // format: on
+  ) ++ unsupportedInstF
+  generator.parameter.decoderParam.allInstructions.filter { instruction: Instruction =>
+    !(unsupportedInst.contains(instruction.name) && generator.parameter.xlen == 32)
+  }.map { instruction: Instruction =>
     val issueMatch = Sequence.BoolSequence(issue.instruction === BitPat("b" + instruction.encoding.toString))
     CoverProperty(issueMatch, label = Some(s"t1_cover_issue_${instruction.name}"))
   }