[emulator] add format for all T1 code

chipsalliance · Oct 5, 2024 · 2983276 · 2983276
1 parent d7395a2
commit 2983276
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Showing 36 changed files with 733 additions and 621 deletions.
diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml
@@ -40,9 +40,15 @@ jobs:
           }
 
           nix develop '.#t1.elaborator' -c mill -i configgen.reformat
+          nix develop '.#t1.elaborator' -c mill -i elaborator.reformat
+          nix develop '.#t1.elaborator' -c mill -i omreader.reformat
+          nix develop '.#t1.elaborator' -c mill -i omreaderlib.reformat
           nix develop '.#t1.elaborator' -c mill -i rocketv.reformat
+          nix develop '.#t1.elaborator' -c mill -i rocketemu.reformat
           nix develop '.#t1.elaborator' -c mill -i t1.reformat
+          nix develop '.#t1.elaborator' -c mill -i t1emu.reformat
           nix develop '.#t1.elaborator' -c mill -i t1rocket.reformat
+          nix develop '.#t1.elaborator' -c mill -i t1rocketemu.reformat
           warnOnFileChanged "* Scala format fail, please run 'nix develop '.#t1.elaborator' -c mill -i _.reformat'"
 
           nix fmt

diff --git a/build.sc b/build.sc
@@ -139,7 +139,7 @@ trait T1Rocket extends millbuild.common.T1RocketModule with ScalafmtModule {
 
 object t1emu extends T1Emulator
 
-trait T1Emulator extends millbuild.common.T1EmulatorModule {
+trait T1Emulator extends millbuild.common.T1EmulatorModule with ScalafmtModule {
   def scalaVersion = T(v.scala)
 
   def t1Module = t1
@@ -151,7 +151,8 @@ trait T1Emulator extends millbuild.common.T1EmulatorModule {
 }
 
 object rocketemu     extends RocketEmulator
-trait RocketEmulator extends millbuild.common.RocketEmulatorModule {
+
+trait RocketEmulator extends millbuild.common.RocketEmulatorModule with ScalafmtModule {
   def scalaVersion = T(v.scala)
 
   def rocketVModule = rocketv
@@ -164,7 +165,7 @@ trait RocketEmulator extends millbuild.common.RocketEmulatorModule {
 
 object t1rocketemu extends T1RocketEmulator
 
-trait T1RocketEmulator extends millbuild.common.T1RocketEmulatorModule {
+trait T1RocketEmulator extends millbuild.common.T1RocketEmulatorModule with ScalafmtModule {
   def scalaVersion = T(v.scala)
 
   def t1rocketModule = t1rocket
@@ -188,7 +189,7 @@ trait PanamaConverter extends millbuild.dependencies.chisel.build.PanamaConverte
 // Module to generate RTL from json config
 object elaborator extends Elaborator
 
-trait Elaborator extends millbuild.common.ElaboratorModule {
+trait Elaborator extends millbuild.common.ElaboratorModule with ScalafmtModule {
   def scalaVersion = T(v.scala)
 
   def panamaconverterModule = panamaconverter
@@ -214,7 +215,7 @@ trait Elaborator extends millbuild.common.ElaboratorModule {
 
 object omreaderlib extends OMReaderLib
 
-trait OMReaderLib extends millbuild.common.OMReaderLibModule {
+trait OMReaderLib extends millbuild.common.OMReaderLibModule with ScalafmtModule {
   def scalaVersion = T(v.scala)
 
   def panamaconverterModule = panamaconverter
@@ -231,7 +232,7 @@ trait OMReaderLib extends millbuild.common.OMReaderLibModule {
 
 object omreader extends OMReader
 
-trait OMReader extends millbuild.common.OMReaderModule {
+trait OMReader extends millbuild.common.OMReaderModule with ScalafmtModule {
   def scalaVersion = T(v.scala)
 
   def panamaconverterModule = panamaconverter

diff --git a/elaborator/src/Elaborator.scala b/elaborator/src/Elaborator.scala
@@ -17,45 +17,48 @@ trait Elaborator {
   }
 
   def configImpl[P <: SerializableModuleParameter: universe.TypeTag](
-                                                                      parameter: P
-                                                                    )(implicit rwP: upickle.default.Writer[P]) = os.write.over(
+    parameter:    P
+  )(
+    implicit rwP: upickle.default.Writer[P]
+  ) = os.write.over(
     os.pwd / s"${getClass.getSimpleName.replace("$", "")}.json",
     upickle.default.write(parameter)
   )
 
-  def designImpl[
-    M <: SerializableModule[P]: universe.TypeTag,
-    P <: SerializableModuleParameter: universe.TypeTag
-  ](parameter: os.Path, runFirtool: Boolean)(implicit
-                                             rwP: upickle.default.Reader[P]
+  def designImpl[M <: SerializableModule[P]: universe.TypeTag, P <: SerializableModuleParameter: universe.TypeTag](
+    parameter:  os.Path,
+    runFirtool: Boolean
+  )(
+    implicit
+    rwP:        upickle.default.Reader[P]
   ) = {
     var fir: firrtl.ir.Circuit = null
-    val annos = Seq(
+    val annos        = Seq(
       new chisel3.stage.phases.Elaborate,
       new chisel3.stage.phases.Convert
     ).foldLeft(
-        Seq(
-          chisel3.stage.ChiselGeneratorAnnotation(() =>
-            SerializableModuleGenerator(
-              runtimeMirror(getClass.getClassLoader)
-                .runtimeClass(typeOf[M].typeSymbol.asClass)
-                .asInstanceOf[Class[M]],
-              upickle.default.read[P](os.read(parameter))
-            ).module().asInstanceOf[RawModule]
-          )
-        ): firrtl.AnnotationSeq
-      ) { case (annos, stage) => stage.transform(annos) }
+      Seq(
+        chisel3.stage.ChiselGeneratorAnnotation(() =>
+          SerializableModuleGenerator(
+            runtimeMirror(getClass.getClassLoader)
+              .runtimeClass(typeOf[M].typeSymbol.asClass)
+              .asInstanceOf[Class[M]],
+            upickle.default.read[P](os.read(parameter))
+          ).module().asInstanceOf[RawModule]
+        )
+      ): firrtl.AnnotationSeq
+    ) { case (annos, stage) => stage.transform(annos) }
       .flatMap {
         case firrtl.stage.FirrtlCircuitAnnotation(circuit) =>
           fir = circuit
           None
         case _: chisel3.stage.DesignAnnotation[_]     => None
         case _: chisel3.stage.ChiselCircuitAnnotation => None
-        case a                                        => Some(a)
+        case a => Some(a)
       }
     val annoJsonFile = os.pwd / s"${fir.main}.anno.json"
-    val firFile = os.pwd / s"${fir.main}.fir"
-    val svFile = os.pwd / s"${fir.main}.sv"
+    val firFile      = os.pwd / s"${fir.main}.fir"
+    val svFile       = os.pwd / s"${fir.main}.sv"
     os.write.over(firFile, fir.serialize)
     os.write.over(
       annoJsonFile,

diff --git a/elaborator/src/Main.scala b/elaborator/src/Main.scala
@@ -20,7 +20,7 @@ object Main {
     @arg(name = "target-dir", short = 't') targetDir: os.Path,
     @arg(name = "binder-mlirbc-out") binderMlirbcOut: Option[String] = None) {
     def elaborate(gen: () => chisel3.RawModule): Unit = {
-      var fir:                  firrtl.ir.Circuit = null
+      var fir:                  firrtl.ir.Circuit                            = null
       var panamaCIRCTConverter: chisel3.panamaconverter.PanamaCIRCTConverter = null
 
       val annos = Seq(
@@ -41,7 +41,7 @@ object Main {
         ): firrtl.AnnotationSeq
       ) { case (annos, stage) => stage.transform(annos) }
         .flatMap {
-          case firrtl.stage.FirrtlCircuitAnnotation(circuit) =>
+          case firrtl.stage.FirrtlCircuitAnnotation(circuit)                           =>
             if (binderMlirbcOut.isEmpty) fir = circuit
             None
           case chisel3.panamaconverter.stage.PanamaCIRCTConverterAnnotation(converter) =>
@@ -56,7 +56,7 @@ object Main {
       binderMlirbcOut match {
         case Some(outFile) =>
           os.write(targetDir / s"$outFile.mlirbc", panamaCIRCTConverter.mlirBytecodeStream)
-        case None =>
+        case None          =>
           os.write(targetDir / s"${fir.main}.fir", fir.serialize)
           os.write(targetDir / s"${fir.main}.anno.json", firrtl.annotations.JsonProtocol.serialize(annos))
       }
@@ -95,8 +95,8 @@ object Main {
     def parameter: T1RocketTileParameter = generator.parameter
   }
 
-  implicit def ipConfig:       ParserForClass[IPConfig] = ParserForClass[IPConfig]
-  implicit def rocketConfig:   ParserForClass[RocketConfig] = ParserForClass[RocketConfig]
+  implicit def ipConfig:       ParserForClass[IPConfig]       = ParserForClass[IPConfig]
+  implicit def rocketConfig:   ParserForClass[RocketConfig]   = ParserForClass[RocketConfig]
   implicit def t1RocketConfig: ParserForClass[T1RocketConfig] = ParserForClass[T1RocketConfig]
 
   @main def ip(elaborateConfig: ElaborateConfig, ipConfig: IPConfig): Unit =

diff --git a/elaborator/src/rocketv/BTB.scala b/elaborator/src/rocketv/BTB.scala
@@ -12,7 +12,7 @@ object BTB extends Elaborator {
     @arg(name = "nEntries") nEntries:           Int,
     @arg(name = "counterLength") counterLength: Int,
     @arg(name = "historyLength") historyLength: Int,
-    @arg(name = "historyBits") historyBits:     Int) {
+    @arg(name = "historyBits") historyBits: Int) {
     def convert: BHTParameter = BHTParameter(
       nEntries,
       counterLength,
@@ -39,8 +39,7 @@ object BTB extends Elaborator {
     @arg(name = "bht-counterLength") counterLength:     Option[Int],
     @arg(name = "bht-historyLength") historyLength:     Option[Int],
     @arg(name = "bht-historyBits") historyBits:         Option[Int],
-    @arg(name = "fetchWidth") fetchWidth:               Int,
-                             ) {
+    @arg(name = "fetchWidth") fetchWidth: Int) {
     def convert: BTBParameter = BTBParameter(
       useAsyncReset,
       fetchBytes,
@@ -58,9 +57,8 @@ object BTB extends Elaborator {
         .lazyZip(counterLength)
         .lazyZip(historyLength)
         .lazyZip(historyBits))
-        .map {
-          case (nEntries, counterLength, historyLength, historyBits) =>
-            BHTParameter(nEntries, counterLength, historyLength, historyBits)
+        .map { case (nEntries, counterLength, historyLength, historyBits) =>
+          BHTParameter(nEntries, counterLength, historyLength, historyBits)
         }
         .headOption
     )

diff --git a/elaborator/src/rocketv/CSR.scala b/elaborator/src/rocketv/CSR.scala
@@ -30,7 +30,7 @@ object CSR extends Elaborator {
     @arg(name = "usingAtomics") usingAtomics:       Boolean,
     @arg(name = "usingDebug") usingDebug:           Boolean,
     @arg(name = "usingMulDiv") usingMulDiv:         Boolean,
-    @arg(name = "usingVector") usingVector:         Boolean) {
+    @arg(name = "usingVector") usingVector: Boolean) {
     def convert: CSRParameter = CSRParameter(
       useAsyncReset:   Boolean,
       vLen:            Int,

diff --git a/elaborator/src/rocketv/DCache.scala b/elaborator/src/rocketv/DCache.scala
@@ -10,7 +10,7 @@ import org.chipsalliance.t1.elaborator.Elaborator
 
 object DCache extends Elaborator {
   implicit object BitSetRead extends TokensReader.Simple[BitSet] {
-    def shortName = "bitset"
+    def shortName               = "bitset"
     def read(strs: Seq[String]) = {
       Right(
         strs.head
@@ -19,13 +19,13 @@ object DCache extends Elaborator {
             if (opt.contains("-")) {
               val range = opt.split("-")
               require(range.size == 2)
-              val from = BigInt(range.head, 16)
-              val to = BigInt(range.last, 16) + 1
+              val from  = BigInt(range.head, 16)
+              val to    = BigInt(range.last, 16) + 1
               BitSet.fromRange(from, to - from, range.head.length * 4)
             } else if (opt.contains("+")) {
-              val range = opt.split("\\+")
+              val range  = opt.split("\\+")
               require(range.size == 2)
-              val from = BigInt(range.head, 16)
+              val from   = BigInt(range.head, 16)
               val length = BigInt(range.last, 16)
               BitSet.fromRange(from, length, range.head.length * 4)
             } else {
@@ -63,7 +63,7 @@ object DCache extends Elaborator {
     @arg(name = "logic") logic:                               BitSet,
     @arg(name = "arithmetic") arithmetic:                     BitSet,
     @arg(name = "exec") exec:                                 BitSet,
-    @arg(name = "sideEffects") sideEffects:                   BitSet) {
+    @arg(name = "sideEffects") sideEffects: BitSet) {
     def convert: HellaCacheParameter = HellaCacheParameter(
       useAsyncReset,
       clockGate,

diff --git a/elaborator/src/rocketv/Decoder.scala b/elaborator/src/rocketv/Decoder.scala
@@ -9,8 +9,8 @@ import org.chipsalliance.t1.elaborator.Elaborator
 object Decoder extends Elaborator {
   @main
   case class DecoderParameterMain(
-    @arg(name = "instructionSets") instructionSets:     Set[String],
-    @arg(name = "pipelinedMul") pipelinedMul:           Boolean,
+    @arg(name = "instructionSets") instructionSets: Set[String],
+    @arg(name = "pipelinedMul") pipelinedMul:       Boolean,
     @arg(name = "fenceIFlushDCache") fenceIFlushDCache: Boolean) {
     def convert: DecoderParameter = DecoderParameter(
       instructionSets,

diff --git a/elaborator/src/rocketv/FPToFP.scala b/elaborator/src/rocketv/FPToFP.scala
@@ -13,7 +13,7 @@ object FPToFP extends Elaborator {
     latency:       Int,
     xLen:          Int,
     fLen:          Int,
-    minFLen:       Int) {
+    minFLen: Int) {
     def convert: FPToFPParameter = FPToFPParameter(
       useAsyncReset,
       latency,

diff --git a/elaborator/src/rocketv/FPToInt.scala b/elaborator/src/rocketv/FPToInt.scala
@@ -12,7 +12,7 @@ object FPToInt extends Elaborator {
     @arg(name = "useAsyncReset") useAsyncReset: Boolean,
     @arg(name = "xLen") xLen:                   Int,
     @arg(name = "fLen") fLen:                   Int,
-    @arg(name = "minFLen") minFLen:             Int) {
+    @arg(name = "minFLen") minFLen: Int) {
     def convert: FPToIntParameter = FPToIntParameter(
       useAsyncReset,
       xLen,

diff --git a/elaborator/src/rocketv/FPU.scala b/elaborator/src/rocketv/FPU.scala
@@ -17,7 +17,7 @@ object FPU extends Elaborator {
     @arg(name = "sfmaLatency") sfmaLatency:       Int,
     @arg(name = "dfmaLatency") dfmaLatency:       Int,
     @arg(name = "divSqrt") divSqrt:               Boolean,
-    @arg(name = "hartIdLen") hartIdLen:           Int) {
+    @arg(name = "hartIdLen") hartIdLen: Int) {
     def convert: FPUParameter = FPUParameter(
       useAsyncReset,
       useClockGating,

diff --git a/elaborator/src/rocketv/FPUFMAPipe.scala b/elaborator/src/rocketv/FPUFMAPipe.scala
@@ -14,7 +14,7 @@ object FPUFMAPipe extends Elaborator {
     xLen:          Int,
     fLen:          Int,
     minFLen:       Int,
-    t:             String) {
+    t: String) {
 
     def convert: FPUFMAPipeParameter = FPUFMAPipeParameter(
       useAsyncReset,

diff --git a/elaborator/src/rocketv/Frontend.scala b/elaborator/src/rocketv/Frontend.scala
@@ -10,7 +10,7 @@ import org.chipsalliance.t1.elaborator.Elaborator
 
 object Frontend extends Elaborator {
   implicit object BitSetRead extends TokensReader.Simple[BitSet] {
-    def shortName = "bitset"
+    def shortName               = "bitset"
     def read(strs: Seq[String]) = {
       Right(
         strs.head
@@ -19,13 +19,13 @@ object Frontend extends Elaborator {
             if (opt.contains("-")) {
               val range = opt.split("-")
               require(range.size == 2)
-              val from = BigInt(range.head, 16)
-              val to = BigInt(range.last, 16) + 1
+              val from  = BigInt(range.head, 16)
+              val to    = BigInt(range.last, 16) + 1
               BitSet.fromRange(from, to - from, range.head.length * 4)
             } else if (opt.contains("+")) {
-              val range = opt.split("\\+")
+              val range  = opt.split("\\+")
               require(range.size == 2)
-              val from = BigInt(range.head, 16)
+              val from   = BigInt(range.head, 16)
               val length = BigInt(range.last, 16)
               BitSet.fromRange(from, length, range.head.length * 4)
             } else {
@@ -76,7 +76,7 @@ object Frontend extends Elaborator {
     @arg(name = "logic") logic:                                 Seq[BitSet],
     @arg(name = "arithmetic") arithmetic:                       Seq[BitSet],
     @arg(name = "exec") exec:                                   Seq[BitSet],
-    @arg(name = "sideEffects") sideEffects:                     Seq[BitSet]) {
+    @arg(name = "sideEffects") sideEffects: Seq[BitSet]) {
     def convert: FrontendParameter = FrontendParameter(
       useAsyncReset:         Boolean,
       clockGate:             Boolean,
@@ -107,9 +107,8 @@ object Frontend extends Elaborator {
         .lazyZip(bhtCounterLength)
         .lazyZip(bhtHistoryLength)
         .lazyZip(bhtHistoryBits)
-        .map {
-          case (bhtNEntries, bhtCounterLength, bhtHistoryLength, bhtHistoryBits) =>
-            BHTParameter(bhtNEntries, bhtCounterLength, bhtHistoryLength, bhtHistoryBits)
+        .map { case (bhtNEntries, bhtCounterLength, bhtHistoryLength, bhtHistoryBits) =>
+          BHTParameter(bhtNEntries, bhtCounterLength, bhtHistoryLength, bhtHistoryBits)
         }
         .headOption,
       legal.foldLeft(BitSet.empty)(_.union(_)),

diff --git a/elaborator/src/rocketv/IBuf.scala b/elaborator/src/rocketv/IBuf.scala
@@ -17,7 +17,7 @@ object IBuf extends Elaborator {
     @arg(name = "vaddrBitsExtended") vaddrBitsExtended: Int,
     @arg(name = "bhtHistoryLength") bhtHistoryLength:   Option[Int],
     @arg(name = "bhtCounterLength") bhtCounterLength:   Option[Int],
-    @arg(name = "fetchWidth") fetchWidth:               Int) {
+    @arg(name = "fetchWidth") fetchWidth: Int) {
     def convert: IBufParameter = IBufParameter(
       useAsyncReset,
       xLen,

diff --git a/elaborator/src/rocketv/ICache.scala b/elaborator/src/rocketv/ICache.scala
@@ -16,7 +16,7 @@ object ICache extends Elaborator {
     @arg(name = "blockBytes") blockBytes:       Int,
     @arg(name = "usingVM") usingVM:             Boolean,
     @arg(name = "vaddrBits") vaddrBits:         Int,
-    @arg(name = "paddrBits") paddrBits:         Int) {
+    @arg(name = "paddrBits") paddrBits: Int) {
     def convert: ICacheParameter = ICacheParameter(
       useAsyncReset,
       prefetch,

diff --git a/elaborator/src/rocketv/IntToFP.scala b/elaborator/src/rocketv/IntToFP.scala
@@ -13,7 +13,7 @@ object IntToFP extends Elaborator {
     @arg(name = "latency") latency:             Int,
     @arg(name = "fLen") fLen:                   Int,
     @arg(name = "xLen") xLen:                   Int,
-    @arg(name = "minFLen") minFLen:             Int) {
+    @arg(name = "minFLen") minFLen: Int) {
     def convert: IntToFPParameter = IntToFPParameter(
       useAsyncReset,
       latency,

diff --git a/elaborator/src/rocketv/MulAddRecFNPipe.scala b/elaborator/src/rocketv/MulAddRecFNPipe.scala
@@ -12,7 +12,7 @@ object MulAddRecFNPipe extends Elaborator {
     @arg(name = "useAsyncReset") useAsyncReset: Boolean,
     @arg(name = "latency") latency:             Int,
     @arg(name = "expWidth") expWidth:           Int,
-    @arg(name = "sigWidth") sigWidth:           Int) {
+    @arg(name = "sigWidth") sigWidth: Int) {
     def convert: MulAddRecFNPipeParameter = MulAddRecFNPipeParameter(useAsyncReset, latency, expWidth, sigWidth)
   }