f om

chipsalliance · Oct 16, 2024 · 288cf2a · 288cf2a
1 parent 9fd0bff
commit 288cf2a
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/t1rocketemu/src/TestBench.scala b/t1rocketemu/src/TestBench.scala
@@ -36,6 +36,7 @@ class TestBench(val parameter: T1RocketTileParameter)
   @public
   val om:         Property[ClassType]   = IO(Output(Property[omType.Type]()))
   om := omInstance.getPropertyReference
+  omInstance.t1RocketTileIn := Property(dut.io.om.asAnyClassType)
 
   val clockGen               = Module(new ExtModule with HasExtModuleInline {
     override def desiredName = "ClockGen"