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fixup! fix sram
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Signed-off-by: Avimitin <[email protected]>
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Avimitin committed Nov 21, 2024
1 parent 200f14b commit 2205294
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Showing 2 changed files with 2 additions and 2 deletions.
2 changes: 1 addition & 1 deletion difftest/dpi_t1rocketemu/src/bus.rs
Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@ impl ShadowBus {
pub fn new() -> Self {
const DDR_SIZE: usize = 0x80000000;
const SCALAR_SIZE: usize = 0x20000000;
const SRAM_SIZE: usize = 0x40000000;
const SRAM_SIZE: usize = 0x32000000;

Self {
devices: [
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2 changes: 1 addition & 1 deletion tests/t1.ld
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ MEMORY {
SCALAR (RWX) : ORIGIN = 0x20000000, LENGTH = 512M /* put first to set it as default */
MMIO (RW) : ORIGIN = 0x00000000, LENGTH = 512M
DDR (RW) : ORIGIN = 0x40000000, LENGTH = 2048M
SRAM (RW) : ORIGIN = 0xc0000000, LENGTH = 1024M /* TODO: read from config */
SRAM (RW) : ORIGIN = 0xc0000000, LENGTH = 800M /* TODO: read from config */
}

SECTIONS {
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