[rtl] fix t1rocket redmin.

chipsalliance · Nov 11, 2024 · 0e74cac · 0e74cac
1 parent eac86ef
commit 0e74cac
Showing 1 changed file with 2 additions and 3 deletions.
diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
@@ -299,9 +299,8 @@ class MaskUnit(parameter: T1Parameter) extends Module {
 
       val dLog = log2Ceil(parameter.datapathWidth/8)
       // How many datapaths does LSB contain?
-      val lsbDSize = (vlLSB >> dLog).asUInt + changeUIntSize(vlLSB, dLog).orR
-      // 0 -UIntToOH> 00001 -( >> 1)> 00000
-      (UIntToOH(lsbDSize) >> 1).asUInt | Fill(parameter.laneNumber, vlMSB)
+      val lsbDSize = (vlLSB >> dLog).asUInt - !changeUIntSize(vlLSB, dLog).orR
+      scanRightOr(UIntToOH(lsbDSize))| Fill(parameter.laneNumber, vlMSB)
     }
   )