[rtl] duplicate v0 in lsu.

chipsalliance · Dec 11, 2024 · 09914a2 · 09914a2
1 parent 0be86ac
commit 09914a2
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Showing 21 changed files with 127 additions and 113 deletions.
diff --git a/rocketv/src/HellaCache.scala b/rocketv/src/HellaCache.scala
@@ -525,7 +525,9 @@ class HellaCache(val parameter: HellaCacheParameter)
         numReadwritePorts = 1
       )
     }
-    omInstance.sramsIn.foreach(_ := Property((dcacheDataSRAM ++ Some(dcacheTagSRAM)).map(_.description.get.asAnyClassType)))
+    omInstance.sramsIn.foreach(
+      _ := Property((dcacheDataSRAM ++ Some(dcacheTagSRAM)).map(_.description.get.asAnyClassType))
+    )
 
     /** Data Arbiter 0: data from pending store buffer 1: data from TL-D refill 2: release to TL-A 3: hit path to CPU
       */

diff --git a/rocketv/src/ICache.scala b/rocketv/src/ICache.scala
@@ -555,7 +555,9 @@ class ICache(val parameter: ICacheParameter)
         numReadwritePorts = 1
       )
     }
-  omInstance.sramsIn.foreach(_ := Property((icacheDataSRAM ++ Some(icacheTagSRAM)).map(_.description.get.asAnyClassType)))
+  omInstance.sramsIn.foreach(
+    _ := Property((icacheDataSRAM ++ Some(icacheTagSRAM)).map(_.description.get.asAnyClassType))
+  )
 
   for ((data_array, i) <- icacheDataSRAM.zipWithIndex) {
 

diff --git a/t1/src/Bundles.scala b/t1/src/Bundles.scala
@@ -360,9 +360,9 @@ class LaneResponseFeedback(param: LaneParameter) extends Bundle {
   val complete: Bool = Bool()
 }
 
-class V0Update(param: LaneParameter) extends Bundle {
-  val data:   UInt = UInt(param.datapathWidth.W)
-  val offset: UInt = UInt(param.vrfOffsetBits.W)
+class V0Update(datapathWidth: Int, vrfOffsetBits: Int) extends Bundle {
+  val data:   UInt = UInt(datapathWidth.W)
+  val offset: UInt = UInt(vrfOffsetBits.W)
   // mask/ld类型的有可能不会写完整的32bit
   val mask:   UInt = UInt(4.W)
 }

diff --git a/t1/src/FloatModule.scala b/t1/src/FloatModule.scala
@@ -4,11 +4,11 @@
 package org.chipsalliance.t1.rtl
 
 import chisel3._
-import chisel3.experimental.{SerializableModule, SerializableModuleParameter, SerializableModuleGenerator}
-import chisel3.experimental.hierarchy.{public, Instance, instantiable, Instantiate}
+import chisel3.experimental.{SerializableModule, SerializableModuleGenerator, SerializableModuleParameter}
+import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate}
 import chisel3.util._
 import chisel3.util.experimental.decode.TruthTable
-import chisel3.properties.{Path, AnyClassType, Property}
+import chisel3.properties.{AnyClassType, Path, Property}
 import hardfloat._
 import org.chipsalliance.stdlib.GeneralOM
 import upickle.default
@@ -52,7 +52,7 @@ class FloatAdder(val parameter: FloatAdderParameter)
   val latency  = parameter.latency
 
   val omInstance: Instance[FloatAdderOM] = Instantiate(new FloatAdderOM(parameter))
-  io.om                   := omInstance.getPropertyReference
+  io.om := omInstance.getPropertyReference
   omInstance.retimeIn.foreach(_ := Property(Path(io.clock)))
 
   val addRecFN = Module(new AddRecFN(expWidth, sigWidth))

diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -276,7 +276,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
 
   /** V0 update in the lane should also update [[T1.v0]] */
   @public
-  val v0Update: ValidIO[V0Update] = IO(Valid(new V0Update(parameter)))
+  val v0Update: ValidIO[V0Update] = IO(Valid(new V0Update(parameter.datapathWidth, parameter.vrfOffsetBits)))
 
   /** input of mask data */
   @public
@@ -371,33 +371,33 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
 
   // todo: mv to bundle.scala
   class MaskControl(parameter: LaneParameter) extends Bundle {
-    val index: UInt = UInt(parameter.instructionIndexBits.W)
-    val sew: UInt = UInt(2.W)
-    val maskData: UInt = UInt(parameter.datapathWidth.W)
-    val group: UInt = UInt(parameter.maskGroupSizeBits.W)
-    val dataValid: Bool = Bool()
+    val index:         UInt = UInt(parameter.instructionIndexBits.W)
+    val sew:           UInt = UInt(2.W)
+    val maskData:      UInt = UInt(parameter.datapathWidth.W)
+    val group:         UInt = UInt(parameter.maskGroupSizeBits.W)
+    val dataValid:     Bool = Bool()
     val waiteResponse: Bool = Bool()
-    val controlValid: Bool = Bool()
+    val controlValid:  Bool = Bool()
   }
 
   val maskControlRelease: Vec[ValidIO[UInt]] =
     Wire(Vec(parameter.chainingSize, Valid(UInt(parameter.instructionIndexBits.W))))
 
-  val maskControlEnq: UInt = Wire(UInt(parameter.chainingSize.W))
-  val maskControlDataDeq: UInt = Wire(UInt(parameter.chainingSize.W))
-  val maskControlReq: Vec[Bool] = Wire(Vec(parameter.chainingSize, Bool()))
-  val maskControlReqSelect: UInt = ffo(maskControlReq.asUInt)
+  val maskControlEnq:       UInt             = Wire(UInt(parameter.chainingSize.W))
+  val maskControlDataDeq:   UInt             = Wire(UInt(parameter.chainingSize.W))
+  val maskControlReq:       Vec[Bool]        = Wire(Vec(parameter.chainingSize, Bool()))
+  val maskControlReqSelect: UInt             = ffo(maskControlReq.asUInt)
   // mask request & response handle
-  val maskControlVec: Seq[MaskControl] = Seq.tabulate(parameter.chainingSize) { index =>
+  val maskControlVec:       Seq[MaskControl] = Seq.tabulate(parameter.chainingSize) { index =>
     val state = RegInit(0.U.asTypeOf(new MaskControl(parameter)))
     val releaseHit: Bool = maskControlRelease.map(r => r.valid && (r.bits === state.index)).reduce(_ || _)
     val responseFire =
       Pipe(maskControlReqSelect(index), 0.U.asTypeOf(new EmptyBundle), parameter.maskRequestLatency).valid
 
     when(maskControlEnq(index)) {
-      state := 0.U.asTypeOf(state)
-      state.index := laneRequest.bits.instructionIndex
-      state.sew := laneRequest.bits.csrInterface.vSew
+      state              := 0.U.asTypeOf(state)
+      state.index        := laneRequest.bits.instructionIndex
+      state.sew          := laneRequest.bits.csrInterface.vSew
       state.controlValid := true.B
     }
 
@@ -410,13 +410,13 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     maskControlReq(index) := state.controlValid && !state.dataValid && !state.waiteResponse
     when(maskControlReqSelect(index)) {
       state.waiteResponse := true.B
-      state.group := state.group + 1.U
+      state.group         := state.group + 1.U
     }
 
     when(responseFire) {
-      state.dataValid := true.B
+      state.dataValid     := true.B
       state.waiteResponse := false.B
-      state.maskData := maskInput
+      state.maskData      := maskInput
     }
 
     when(maskControlDataDeq(index)) {
@@ -425,8 +425,8 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
 
     state
   }
-  val maskControlFree: Seq[Bool] = maskControlVec.map(s => !s.controlValid && !s.waiteResponse)
-  val freeSelect: UInt = ffo(VecInit(maskControlFree).asUInt)
+  val maskControlFree:      Seq[Bool]        = maskControlVec.map(s => !s.controlValid && !s.waiteResponse)
+  val freeSelect:           UInt             = ffo(VecInit(maskControlFree).asUInt)
   maskControlEnq := maskAnd(laneRequest.fire && laneRequest.bits.mask, freeSelect)
 
   /** for each slot, assert when it is asking [[T1]] to change mask */
@@ -439,7 +439,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
 
   /** which slot wins the arbitration for requesting mask. */
   val maskRequestFireOH: Vec[Bool] = Wire(Vec(parameter.chainingSize, Bool()))
-  val maskDataVec: Vec[UInt] = Wire(Vec(parameter.chainingSize, UInt(parameter.maskGroupWidth.W)))
+  val maskDataVec:       Vec[UInt] = Wire(Vec(parameter.chainingSize, UInt(parameter.maskGroupWidth.W)))
 
   /** FSM control for each slot. if index == 0,
     *   - slot can support write v0 in mask type, see [[Decoder.maskDestination]] [[Decoder.maskSource]]
@@ -663,14 +663,14 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     }
 
     maskControlRelease(index).valid := false.B
-    maskControlRelease(index).bits := record.laneRequest.instructionIndex
+    maskControlRelease(index).bits  := record.laneRequest.instructionIndex
     // update lane state
     when(stage0.enqueue.fire) {
       maskGroupCountVec(index) := stage0.updateLaneState.maskGroupCount
       // todo: handle all elements in first group are masked
       maskIndexVec(index)      := stage0.updateLaneState.maskIndex
       when(stage0.updateLaneState.outOfExecutionRange) {
-        slotOccupied(index) := false.B
+        slotOccupied(index)             := false.B
         maskControlRelease(index).valid := true.B
       }
     }
@@ -962,19 +962,19 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
   }
 
   {
-    maskSelect := Mux1H(maskControlReqSelect, maskControlVec.map(_.group))
-    maskSelectSew := Mux1H(maskControlReqSelect, maskControlVec.map(_.sew))
+    maskSelect         := Mux1H(maskControlReqSelect, maskControlVec.map(_.group))
+    maskSelectSew      := Mux1H(maskControlReqSelect, maskControlVec.map(_.sew))
     maskControlDataDeq := slotMaskRequestVec.zipWithIndex.map { case (req, index) =>
-      val slotIndex = slotControl(index).laneRequest.instructionIndex
-      val hitMaskControl = VecInit(maskControlVec.map(_.index === slotIndex)).asUInt
-      val dataValid = Mux1H(hitMaskControl, maskControlVec.map(_.dataValid))
-      val data = Mux1H(hitMaskControl, maskControlVec.map(_.maskData))
-      val group = Mux1H(hitMaskControl, maskControlVec.map(_.group))
-      val sameGroup = group === req.bits
+      val slotIndex       = slotControl(index).laneRequest.instructionIndex
+      val hitMaskControl  = VecInit(maskControlVec.map(_.index === slotIndex)).asUInt
+      val dataValid       = Mux1H(hitMaskControl, maskControlVec.map(_.dataValid))
+      val data            = Mux1H(hitMaskControl, maskControlVec.map(_.maskData))
+      val group           = Mux1H(hitMaskControl, maskControlVec.map(_.group))
+      val sameGroup       = group === req.bits
       dontTouch(sameGroup)
       val maskRequestFire = req.valid && dataValid
       maskRequestFireOH(index) := maskRequestFire
-      maskDataVec(index) := data
+      maskDataVec(index)       := data
       maskAnd(maskRequestFire, hitMaskControl).asUInt
     }.reduce(_ | _)
   }

diff --git a/t1/src/LaneAdder.scala b/t1/src/LaneAdder.scala
@@ -4,7 +4,7 @@
 package org.chipsalliance.t1.rtl
 
 import chisel3._
-import chisel3.experimental.hierarchy.{Instance, instantiable, Instantiate}
+import chisel3.experimental.hierarchy.{instantiable, Instance, Instantiate}
 import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
 import chisel3.properties.{Path, Property}
 import chisel3.util._
@@ -54,21 +54,19 @@ class LaneAdderOM(parameter: LaneAdderParam) extends GeneralOM[LaneAdderParam, L
   *   1. 判断大小的结果
   */
 @instantiable
-class LaneAdder(val parameter: LaneAdderParam)
-    extends VFUModule
-    with SerializableModule[LaneAdderParam] {
+class LaneAdder(val parameter: LaneAdderParam) extends VFUModule with SerializableModule[LaneAdderParam] {
   override val omInstance: Instance[LaneAdderOM] = Instantiate(new LaneAdderOM(parameter))
   omInstance.retimeIn.foreach(_ := Property(Path(clock)))
 
-  val response:            LaneAdderResp                      = Wire(new LaneAdderResp(parameter.datapathWidth))
-  val request:             LaneAdderReq                       = connectIO(response).asTypeOf(parameter.inputBundle)
+  val response:      LaneAdderResp = Wire(new LaneAdderResp(parameter.datapathWidth))
+  val request:       LaneAdderReq  = connectIO(response).asTypeOf(parameter.inputBundle)
   // todo: decode
   // ["add", "sub", "slt", "sle", "sgt", "sge", "max", "min", "seq", "sne", "adc", "sbc"]
-  val uopOH:               UInt                               = UIntToOH(request.opcode)(11, 0)
-  val isSub:               Bool                               = !(uopOH(0) || uopOH(10))
+  val uopOH:         UInt          = UIntToOH(request.opcode)(11, 0)
+  val isSub:         Bool          = !(uopOH(0) || uopOH(10))
   // sub -> src(1) - src(0)
-  val subOperation0:       UInt                               = Mux(isSub && !request.reverse, (~request.src.head).asUInt, request.src.head)
-  val subOperation1:       UInt                               = Mux(isSub && request.reverse, (~request.src.last).asUInt, request.src.last)
+  val subOperation0: UInt          = Mux(isSub && !request.reverse, (~request.src.head).asUInt, request.src.head)
+  val subOperation1: UInt          = Mux(isSub && request.reverse, (~request.src.last).asUInt, request.src.last)
   // sub + 1 || carry || borrow
   val operation2 = Fill(4, isSub) ^ request.mask
   val vSewOrR: Bool = request.vSew.orR

diff --git a/t1/src/LaneDiv.scala b/t1/src/LaneDiv.scala
@@ -4,9 +4,9 @@
 package org.chipsalliance.t1.rtl
 
 import chisel3._
-import chisel3.experimental.hierarchy.{public, Instance, instantiable, Instantiate}
+import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate}
 import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
-import chisel3.properties.{Property, Path}
+import chisel3.properties.{Path, Property}
 import chisel3.util._
 import division.srt.{SRT, SRTOutput}
 import org.chipsalliance.stdlib.GeneralOM
@@ -43,10 +43,10 @@ class LaneDivOM(parameter: LaneDivParam) extends GeneralOM[LaneDivParam, LaneDiv
 
 @instantiable
 class LaneDiv(val parameter: LaneDivParam) extends VFUModule with SerializableModule[LaneDivParam] {
-  val omInstance: Instance[LaneDivOM] = Instantiate(new LaneDivOM(parameter))
-  val response:      LaneDivResponse = Wire(new LaneDivResponse(parameter.datapathWidth))
-  val responseValid: Bool            = Wire(Bool())
-  val request:       LaneDivRequest  = connectIO(response, responseValid).asTypeOf(parameter.inputBundle)
+  val omInstance:    Instance[LaneDivOM] = Instantiate(new LaneDivOM(parameter))
+  val response:      LaneDivResponse     = Wire(new LaneDivResponse(parameter.datapathWidth))
+  val responseValid: Bool                = Wire(Bool())
+  val request:       LaneDivRequest      = connectIO(response, responseValid).asTypeOf(parameter.inputBundle)
 
   val wrapper = Instantiate(new SRTWrapper)
   wrapper.input.bits.dividend := request.src.last.asSInt

diff --git a/t1/src/LaneDivFP.scala b/t1/src/LaneDivFP.scala
@@ -4,7 +4,7 @@
 package org.chipsalliance.t1.rtl
 
 import chisel3._
-import chisel3.experimental.hierarchy.{public, Instance, instantiable, Instantiate}
+import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate}
 import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
 import chisel3.util._
 import float._
@@ -46,10 +46,10 @@ class LaneDivFPOM(parameter: LaneDivFPParam) extends GeneralOM[LaneDivFPParam, L
 
 @instantiable
 class LaneDivFP(val parameter: LaneDivFPParam) extends VFUModule with SerializableModule[LaneDivFPParam] {
-  val omInstance: Instance[LaneDivFPOM] = Instantiate(new LaneDivFPOM(parameter))
-  val response:      LaneDivFPResponse = Wire(new LaneDivFPResponse(parameter.datapathWidth))
-  val responseValid: Bool              = Wire(Bool())
-  val request:       LaneDivFPRequest  = connectIO(response, responseValid).asTypeOf(parameter.inputBundle)
+  val omInstance:    Instance[LaneDivFPOM] = Instantiate(new LaneDivFPOM(parameter))
+  val response:      LaneDivFPResponse     = Wire(new LaneDivFPResponse(parameter.datapathWidth))
+  val responseValid: Bool                  = Wire(Bool())
+  val request:       LaneDivFPRequest      = connectIO(response, responseValid).asTypeOf(parameter.inputBundle)
 
   val uop = request.opcode
 

diff --git a/t1/src/LaneFloat.scala b/t1/src/LaneFloat.scala
@@ -3,7 +3,7 @@
 
 package org.chipsalliance.t1.rtl
 
-import chisel3.experimental.hierarchy.{Instance, instantiable, Instantiate}
+import chisel3.experimental.hierarchy.{instantiable, Instance, Instantiate}
 import chisel3.{UInt, _}
 import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
 import chisel3.util._
@@ -57,7 +57,7 @@ class LaneFloatResponse(datapathWidth: Int) extends VFUPipeBundle {
   val executeIndex: UInt = UInt(2.W)
 }
 
-class LaneFloatOM(parameter: LaneFloatParam) extends GeneralOM[LaneFloatParam, LaneFloat](parameter){
+class LaneFloatOM(parameter: LaneFloatParam) extends GeneralOM[LaneFloatParam, LaneFloat](parameter) {
   override def hasRetime: Boolean = true
 }
 
@@ -282,7 +282,11 @@ class LaneFloat(val parameter: LaneFloatParam) extends VFUModule with Serializab
     )
   )
 
-  otherFlags := Mux(rec7En, rec7Module.io.out.exceptionFlags, Mux(rsqrt7En, rsqrt7Module.io.out.exceptionFlags, convertFlags))
+  otherFlags := Mux(
+    rec7En,
+    rec7Module.io.out.exceptionFlags,
+    Mux(rsqrt7En, rsqrt7Module.io.out.exceptionFlags, convertFlags)
+  )
 
   /** collect results */
   result := Mux1H(

diff --git a/t1/src/LaneLogic.scala b/t1/src/LaneLogic.scala
@@ -5,7 +5,7 @@ package org.chipsalliance.t1.rtl
 
 import chisel3._
 import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
-import chisel3.experimental.hierarchy.{Instance, instantiable, Instantiate}
+import chisel3.experimental.hierarchy.{instantiable, Instance, Instantiate}
 import chisel3.util.BitPat
 import chisel3.util.experimental.decode.TruthTable
 import org.chipsalliance.t1.rtl.decoder.TableGenerator

diff --git a/t1/src/LaneMul.scala b/t1/src/LaneMul.scala
@@ -4,9 +4,9 @@
 package org.chipsalliance.t1.rtl
 
 import chisel3._
-import chisel3.experimental.hierarchy.{Instance, instantiable, Instantiate}
+import chisel3.experimental.hierarchy.{instantiable, Instance, Instantiate}
 import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
-import chisel3.properties.{Property, Path}
+import chisel3.properties.{Path, Property}
 import chisel3.util._
 import org.chipsalliance.stdlib.GeneralOM
 import org.chipsalliance.t1.rtl.decoder.{BoolField, Decoder}
@@ -42,7 +42,7 @@ class LaneMulResponse(parameter: LaneMulParam) extends VFUPipeBundle {
   val vxsat: Bool = Bool()
 }
 
-class LaneMulOM(parameter: LaneMulParam) extends GeneralOM[LaneMulParam, LaneMul](parameter){
+class LaneMulOM(parameter: LaneMulParam) extends GeneralOM[LaneMulParam, LaneMul](parameter) {
   override def hasRetime: Boolean = true
 }
 

diff --git a/t1/src/LaneShifter.scala b/t1/src/LaneShifter.scala
@@ -4,7 +4,7 @@
 package org.chipsalliance.t1.rtl
 
 import chisel3._
-import chisel3.experimental.hierarchy.{instantiable, Instantiate, Instance}
+import chisel3.experimental.hierarchy.{instantiable, Instance, Instantiate}
 import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
 import chisel3.properties.{Path, Property}
 import chisel3.util._
@@ -40,9 +40,7 @@ class LaneShifterOM(parameter: LaneShifterParameter) extends GeneralOM[LaneShift
 }
 
 @instantiable
-class LaneShifter(val parameter: LaneShifterParameter)
-    extends VFUModule
-    with SerializableModule[LaneShifterParameter] {
+class LaneShifter(val parameter: LaneShifterParameter) extends VFUModule with SerializableModule[LaneShifterParameter] {
   val omInstance: Instance[LaneShifterOM] = Instantiate(new LaneShifterOM(parameter))
   omInstance.retimeIn.foreach(_ := Property(Path(clock)))
 

diff --git a/t1/src/LaneZvbb.scala b/t1/src/LaneZvbb.scala
@@ -3,7 +3,7 @@
 
 package org.chipsalliance.t1.rtl
 
-import chisel3.experimental.hierarchy.{instantiable, Instantiate, Instance}
+import chisel3.experimental.hierarchy.{instantiable, Instance, Instantiate}
 import chisel3._
 import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
 import chisel3.properties.{Path, Property}

diff --git a/t1/src/MaskedLogic.scala b/t1/src/MaskedLogic.scala
@@ -4,13 +4,13 @@
 package org.chipsalliance.t1.rtl
 
 import chisel3._
-import chisel3.experimental.hierarchy.{Instance, instantiable, Instantiate}
+import chisel3.experimental.hierarchy.{instantiable, Instance, Instantiate}
 import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
-import chisel3.properties.{Property, Path}
+import chisel3.properties.{Path, Property}
 import chisel3.util.BitPat
 import chisel3.util.experimental.decode.TruthTable
 import org.chipsalliance.stdlib.GeneralOM
-import org.chipsalliance.t1.rtl.decoder.{BoolField, TableGenerator, Decoder}
+import org.chipsalliance.t1.rtl.decoder.{BoolField, Decoder, TableGenerator}
 
 object LogicParam {
   implicit def rw: upickle.default.ReadWriter[LogicParam] = upickle.default.macroRW