[om] add SRAM Path to VRF

chipsalliance · Oct 13, 2024 · 05360fa · 05360fa
1 parent 027bcec
commit 05360fa
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Showing 3 changed files with 33 additions and 1 deletion.
diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -27,6 +27,11 @@ class LaneOM extends Class {
   @public
   val vfusIn = IO(Input(Property[Seq[AnyClassType]]()))
   vfus := vfusIn
+  @public
+  val vrf   = IO(Output(Property[AnyClassType]()))
+  @public
+  val vrfIn = IO(Input(Property[AnyClassType]()))
+  vrf := vrfIn
 }
 
 class LaneSlotProbe(instructionIndexBits: Int) extends Bundle {
@@ -321,6 +326,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
 
   /** VRF instantces. */
   val vrf: Instance[VRF] = Instantiate(new VRF(parameter.vrfParam))
+  omInstance.vrfIn := Property(vrf.om.asAnyClassType)
 
   /** TODO: review later
     */

diff --git a/t1/src/VectorFunctionUnit.scala b/t1/src/VectorFunctionUnit.scala
@@ -34,6 +34,11 @@ class VFUOM extends Class {
   @public
   val cyclesIn = IO(Input(Property[Int]()))
   cycles := cyclesIn
+  @public
+  val clock   = IO(Output(Property[Path]))
+  @public
+  val clockIn = IO(Input(Property[Path]))
+  clock := clockIn
 }
 
 @instantiable
@@ -48,7 +53,9 @@ abstract class VFUModule(p: VFUParameter) extends Module {
   @public
   val responseIO: DecoupledIO[VFUPipeBundle] = IO(Decoupled(p.outputBundle))
   om                  := omInstance.getPropertyReference
-  omInstance.cyclesIn := Property(p.latency)
+  // I don't under the parameter of VFU, dirty hack
+  omInstance.cyclesIn := Property(if (p.singleCycle) 1 else 0)
+  omInstance.clockIn  := Property(Path(clock))
 
   val vfuRequestReady: Option[Bool]  = Option.when(!p.singleCycle)(Wire(Bool()))
   val requestReg:      VFUPipeBundle = RegEnable(requestIO.bits, 0.U.asTypeOf(requestIO.bits), requestIO.fire)

diff --git a/t1/src/vrf/VRF.scala b/t1/src/vrf/VRF.scala
@@ -4,12 +4,14 @@
 package org.chipsalliance.t1.rtl.vrf
 
 import chisel3._
+import chisel3.experimental.hierarchy.Instance
 import chisel3.experimental.hierarchy.{instantiable, public, Instantiate}
 import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
 import chisel3.probe.{define, Probe, ProbeValue}
 import chisel3.util._
 import chisel3.ltl._
 import chisel3.ltl.Sequence._
+import chisel3.properties.{AnyClassType, Class, ClassType, Path, Property}
 import org.chipsalliance.t1.rtl.{
   ffo,
   instIndexL,
@@ -117,6 +119,15 @@ case class VRFParam(
   val vrfReadLatency = 2
 }
 
+@instantiable
+class VRFOM extends Class {
+  val srams = IO(Output(Property[Seq[AnyClassType]]()))
+
+  @public
+  val sramsIn = IO(Input(Property[Seq[AnyClassType]]()))
+  srams := sramsIn
+}
+
 class VRFProbe(parameter: VRFParam) extends Bundle {
   val valid:              Bool = Bool()
   val requestVd:          UInt = UInt(parameter.regNumBits.W)
@@ -236,6 +247,12 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
   @public
   val vrfProbe = IO(Output(Probe(new VRFProbe(parameter), layers.Verification)))
 
+  val omInstance: Instance[VRFOM]     = Instantiate(new VRFOM)
+  val omType:     ClassType           = omInstance.toDefinition.getClassType
+  @public
+  val om:         Property[ClassType] = IO(Output(Property[AnyClassType]()))
+  om := omInstance.getPropertyReference.asAnyClassType
+
   // reset sram
   val sramReady:      Bool = RegInit(false.B)
   val sramResetCount: UInt = RegInit(0.U(log2Ceil(parameter.rfDepth).W))
@@ -479,6 +496,8 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
     rf
   }
 
+  omInstance.sramsIn := Property(rfVec.map(_.description.get.asAnyClassType))
+
   val initRecord: ValidIO[VRFWriteReport] = WireDefault(0.U.asTypeOf(Valid(new VRFWriteReport(parameter))))
   initRecord.valid := true.B
   initRecord.bits  := instructionWriteReport.bits