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Fix assign stmt #2143

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alaindargelas
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);

always_comb begin
logic temp = 0;

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]

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I believe this hasn't been addressed

Suggested change
logic temp = 0;
logic temp = 0;

temp = b;
end

endmodule

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]

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similar here

Suggested change
endmodule
endmodule

@kgugala
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kgugala commented Nov 15, 2023

LGTM, @alaindargelas can you address linter comments, so we can merge this?

@pgielda
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pgielda commented Dec 1, 2023

@alaindargelas you've resolved the linter bot without actually addressing the issues?
Also needs rebasing.

@kgugala
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kgugala commented Dec 1, 2023

@alaindargelas please fix the trailing spaces issues pointed out by the linter so we can merge this. Also, this PR needs rebasing as Surelog submodule has been bumped by dependabot in the meantime

@alaindargelas alaindargelas deleted the fix_assign_stmt branch January 11, 2024 22:55
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4 participants