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This bumps Yosys solving the issue with recent changes in the mainline: #1961 I've adjusted the references to Yosys' functions so that the plugin compiles. There are Parsing Tests in Synlig which run simulation. Right now Yosys fails simulation if there are blackboxes. In such cases we should get rid of the simulation part. Some tests are added to the skiplist as Yosys is unable to produce results that would be used in the Formal Verification tests.
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Original file line number | Diff line number | Diff line change |
---|---|---|
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@@ -3,4 +3,3 @@ source ../yosys_common.tcl | |
prep -top \\top | ||
write_verilog | ||
write_verilog yosys.sv | ||
sim -rstlen 10 -vcd dump.vcd |
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Original file line number | Diff line number | Diff line change |
---|---|---|
|
@@ -3,4 +3,3 @@ source ../yosys_common.tcl | |
prep -top \\top | ||
write_verilog | ||
write_verilog yosys.sv | ||
sim -rstlen 10 -vcd dump.vcd |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
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Original file line number | Diff line number | Diff line change |
---|---|---|
|
@@ -3,4 +3,3 @@ source ../yosys_common.tcl | |
prep -top \\top | ||
write_verilog | ||
write_verilog yosys.sv | ||
sim -rstlen 10 -vcd dump.vcd |
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