Update outdated naming (#2686)

This PR updates naming to match `synlig`.

src/frontends/systemverilog/uhdm_ast.cc

@@ -30,7 +30,7 @@ extern bool sv_mode;
 }
 YOSYS_NAMESPACE_END
 
-namespace systemverilog_plugin
+namespace Synlig
 {
 
 using namespace ::Yosys;
@@ -75,7 +75,7 @@ static IdString enum_struct_item;
 /*static*/ const IdString &UhdmAst::low_high_bound() { return attr_id::low_high_bound; }
 /*static*/ const IdString &UhdmAst::is_elaborated_module() { return attr_id::is_elaborated_module; }
 
-#define MAKE_INTERNAL_ID(X) IdString("$systemverilog_plugin$" #X)
+#define MAKE_INTERNAL_ID(X) IdString("$synlig$" #X)
 
 void attr_id_init()
 {
@@ -88,6 +88,7 @@ void attr_id_init()
 
     // Register IdStrings. Can't be done statically, as the IdString class uses resources created during Yosys initialization which happens after
     // static initialization of the plugin when everything is statically linked.
+    // This applies only to Synlig compiled as plugin.
     attr_id::partial = MAKE_INTERNAL_ID(partial);
     attr_id::packed_ranges = MAKE_INTERNAL_ID(packed_ranges);
     attr_id::unpacked_ranges = MAKE_INTERNAL_ID(unpacked_ranges);
@@ -149,7 +150,7 @@ static void delete_attribute(AST::AstNode *node, const IdString &attribute)
     }
 }
 
-// Delete all attributes that belong to the SV plugin.
+// Delete all attributes that belong to the Synlig.
 // The attributes beloning to Yosys are *not* deleted here.
 static void delete_internal_attributes(AST::AstNode *node)
 {
@@ -1371,7 +1372,7 @@ void resolve_children_reparent(AST::AstNode *current_node)
 }
 
 // A wrapper for Yosys simplify function.
-// Simplifies AST constructs specific to this plugin to a form understandable by Yosys' simplify and then calls the latter if necessary.
+// Simplifies AST constructs specific to Synlig to a form understandable by Yosys' simplify and then calls the latter if necessary.
 // Since simplify from Yosys has been forked to this codebase, all new code should be added there instead.
 static void simplify_sv(AST::AstNode *current_node, AST::AstNode *parent_node)
 {
@@ -1836,7 +1837,7 @@ AST::AstNode *UhdmAst::process_value(vpiHandle obj_h)
         }
         // handle vpiBinStrVal, vpiDecStrVal and vpiHexStrVal
         if (val_str.find('\'') != std::string::npos) {
-            return ::systemverilog_plugin::synlig_const2ast(std::move(val_str), caseType, false);
+            return ::Synlig::synlig_const2ast(std::move(val_str), caseType, false);
         } else {
             auto size = vpi_get(vpiSize, obj_h);
             std::string size_str;
@@ -1852,7 +1853,7 @@ AST::AstNode *UhdmAst::process_value(vpiHandle obj_h)
                     size_str = "1";
                 }
             }
-            auto c = ::systemverilog_plugin::synlig_const2ast(size_str + strValType + val_str, caseType, false);
+            auto c = ::Synlig::synlig_const2ast(size_str + strValType + val_str, caseType, false);
             if (size <= 0) {
                 // unsized unbased const
                 c->is_unsized = true;
@@ -2914,7 +2915,7 @@ void UhdmAst::process_enum_typespec()
     }
     if (current_node->str.empty()) {
         // anonymous typespec
-        std::string typedef_name = "$systemverilog_plugin$anonymous_enum" + std::to_string(shared.next_anonymous_enum_typedef_id());
+        std::string typedef_name = "$synlig$anonymous_enum" + std::to_string(shared.next_anonymous_enum_typedef_id());
         current_node->str = typedef_name;
         uhdmast_assert(shared.current_top_node != nullptr);
         move_type_to_new_typedef(shared.current_top_node, current_node);
@@ -3993,7 +3994,7 @@ void UhdmAst::process_stream_op()
     // Get a prefix for internal identifiers.
     const auto stream_op_id = shared.next_loop_id();
     const auto make_id_str = [stream_op_id](const char *suffix) {
-        return std::string("$systemverilog_plugin$stream_op_") + std::to_string(stream_op_id) + "_" + suffix;
+        return std::string("$synlig$stream_op_") + std::to_string(stream_op_id) + "_" + suffix;
     };
 
     if (is_proc_ctx) {
@@ -5771,4 +5772,4 @@ void UhdmAst::report_error(const char *format, ...) const
     }
 }
 
-} // namespace systemverilog_plugin
+} // namespace Synlig

src/frontends/systemverilog/uhdm_ast.h

@@ -9,7 +9,7 @@
 #include <memory>
 #include <uhdm/uhdm.h>
 
-namespace systemverilog_plugin
+namespace Synlig
 {
 
 class AstNodeBuilder;
@@ -330,6 +330,6 @@ class AstNodeBuilder
     operator std::unique_ptr<AstNode>() { return std::move(node); }
 };
 
-} // namespace systemverilog_plugin
+} // namespace Synlig
 
 #endif

src/frontends/systemverilog/uhdm_ast_frontend.cc

@@ -21,7 +21,7 @@
 #include "uhdm/vpi_visitor.h"  // visit_object
 #include "uhdm_common_frontend.h"
 
-namespace systemverilog_plugin
+namespace Synlig
 {
 
 using namespace ::Yosys;
@@ -60,4 +60,4 @@ struct UhdmAstFrontend : public UhdmCommonFrontend {
     void call_log_header(RTLIL::Design *design) override { log_header(design, "Executing UHDM frontend.\n"); }
 } UhdmAstFrontend;
 
-} // namespace systemverilog_plugin
+} // namespace Synlig

src/frontends/systemverilog/uhdm_ast_shared.h

@@ -12,7 +12,7 @@
 #include <uhdm/vpi_user.h>
 #include <unordered_map>
 
-namespace systemverilog_plugin
+namespace Synlig
 {
 
 class UhdmAstShared
@@ -106,6 +106,6 @@ class UhdmAstShared
     std::unordered_map<std::string, std::unordered_map<const UHDM::enum_typespec *, std::string>> anonymous_enums;
 };
 
-} // namespace systemverilog_plugin
+} // namespace Synlig
 
 #endif

src/frontends/systemverilog/uhdm_common_frontend.cc

@@ -35,7 +35,7 @@ extern void process(Design *, AstNode *, bool, bool, bool, bool, bool, bool, boo
 } // namespace Yosys
 #endif
 
-namespace systemverilog_plugin
+namespace Synlig
 {
 
 using namespace ::Yosys;
@@ -194,4 +194,4 @@ void UhdmCommonFrontend::execute(std::istream *&f, std::string filename, std::ve
     }
 }
 
-} // namespace systemverilog_plugin
+} // namespace Synlig

src/frontends/systemverilog/uhdm_common_frontend.h

@@ -26,7 +26,7 @@
 #include <type_traits>
 #include <vector>
 
-namespace systemverilog_plugin
+namespace Synlig
 {
 
 // FIXME (mglb): temporary fix to support UHDM both before and after the following change:
@@ -57,4 +57,4 @@ struct UhdmCommonFrontend : public ::Yosys::Frontend {
     void execute(std::istream *&f, std::string filename, std::vector<std::string> args, ::Yosys::RTLIL::Design *design);
 };
 
-} // namespace systemverilog_plugin
+} // namespace Synlig

src/frontends/systemverilog/uhdm_surelog_ast_frontend.cc

@@ -40,7 +40,7 @@
 #include "uhdm/uhdm-version.h" // UHDM_VERSION define
 #include "uhdm/vpi_visitor.h"  // visit_object
 
-namespace systemverilog_plugin
+namespace Synlig
 {
 
 using namespace ::Yosys;
@@ -399,4 +399,4 @@ struct SystemVerilogDefines : public Pass {
     }
 } SystemVerilogDefines;
 
-} // namespace systemverilog_plugin
+} // namespace Synlig

src/frontends/systemverilog/utils/memory.h

@@ -4,7 +4,7 @@
 #include <cassert>
 #include <utility>
 
-namespace systemverilog_plugin
+namespace Synlig
 {
 
 // `std::default_delete` equivalent for any range of pointers, e.g. `std::vector<Object *>`.
@@ -190,6 +190,6 @@ inline unique_resource<Resource, Deleter> make_unique_resource(Tn &&...arg_n)
     return unique_resource<Resource, Deleter>(Resource(std::forward<Tn>(arg_n)...));
 }
 
-} // namespace systemverilog_plugin
+} // namespace Synlig
 
 #endif // SYSTEMVERILOG_PLUGIN_UTILS_MEMORY_H_

src/mods/yosys_ast/README

@@ -9,14 +9,14 @@ Copied files, their sources, changes & notes:
   - Changes:
     - C++ includes adapted to not rely on `verilog_frontend.h` file.
     - Removed Yosys namespace; `const2ast()` has been placed inside
-      `systemverilog_plugin` namespace to avoid conflicts with the symbol from
+      `Synlig` namespace to avoid conflicts with the symbol from
       Yosys when statically linking.
     - Renamed to synlig_const2ast.cc to prevent GDB breakpoint aliasing from one
       file to the other original file
 - synlig_simplify.cc: yosys/frontends/ast/simplify.cc (rev. ceef00c)
-  - The file is a part of Yosys AST frontend. It has been placed in the plugin,
+  - The file is a part of Yosys AST frontend. It has been placed in Synlig,
     as in some cases we need to adjust it to support certain functionalities
-    in the plugin. Since it is included now in the plugin, we can skip caling
+    in Synlig. Since it is included now in the plugin, we can skip caling
     the original Yosys' simplify() during AST preparation. The original Yosys'
     simplify() is only called in uhdmcommonfrontend.cc when Yosys' process()
     is called, after having AST done.
@@ -36,4 +36,4 @@ Non-copied files placed here for interfacing purposes:
 
 - const2ast.h
 - simplify.h
-- edif.h
+- edif.h

src/mods/yosys_ast/synlig_const2ast.cc

@@ -153,7 +153,7 @@ static void synlig_strtobin(std::vector<RTLIL::State> &data, const char *str, in
 }
 
 // convert the Verilog code for a constant to an AST node
-AstNode *systemverilog_plugin::synlig_const2ast(std::string code, char case_type, bool warn_z)
+AstNode *Synlig::synlig_const2ast(std::string code, char case_type, bool warn_z)
 {
     if (warn_z) {
         AstNode *ret = synlig_const2ast(code, case_type);

src/mods/yosys_ast/synlig_const2ast.h

@@ -4,10 +4,10 @@
 #include "frontends/ast/ast.h"
 #include <string>
 
-namespace systemverilog_plugin
+namespace Synlig
 {
 // this function converts a Verilog constant to an AST_CONSTANT node
 Yosys::AST::AstNode *synlig_const2ast(std::string code, char case_type = 0, bool warn_z = false);
-} // namespace systemverilog_plugin
+} // namespace Synlig
 
 #endif // SYSTEMVERILOG_PLUGIN_CONST2AST_H

src/mods/yosys_ast/synlig_edif.cc

@@ -27,7 +27,7 @@
 #include "kernel/sigtools.h"
 #include <string>
 
-namespace systemverilog_plugin
+namespace Synlig
 {
 
 using namespace ::Yosys;
@@ -618,4 +618,4 @@ void register_synlig_edif_backend()
     seb->init_register();
 }
 
-} // namespace systemverilog_plugin
+} // namespace Synlig

src/mods/yosys_ast/synlig_edif.h

@@ -1,4 +1,4 @@
-namespace systemverilog_plugin
+namespace Synlig
 {
 void register_synlig_edif_backend();
 }

src/mods/yosys_ast/synlig_simplify.cc

@@ -45,7 +45,7 @@ extern bool sv_mode;
 }
 YOSYS_NAMESPACE_END
 
-namespace systemverilog_plugin
+namespace Synlig
 {
 
 using namespace ::Yosys;
@@ -2579,7 +2579,7 @@ bool synlig_simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zer
         int source_width = ast_node->children[0]->id2ast->range_left - ast_node->children[0]->id2ast->range_right + 1;
         int source_offset = ast_node->children[0]->id2ast->range_right;
         int result_width = 1;
-        Yosys::AST::AstNode *member_node = systemverilog_plugin::synlig_get_struct_member(ast_node->children[0]);
+        Yosys::AST::AstNode *member_node = Synlig::synlig_get_struct_member(ast_node->children[0]);
         if (member_node) {
             // Clamp chunk to range of member within struct/union.
             log_assert(!source_offset && !ast_node->children[0]->id2ast->range_swapped);
@@ -3359,7 +3359,7 @@ skip_dynamic_range_lvalue_expansion:;
                                        buf->str.c_str());
 
                     // Check for item in packed struct / union
-                    Yosys::AST::AstNode *item_node = systemverilog_plugin::synlig_get_struct_member(buf);
+                    Yosys::AST::AstNode *item_node = Synlig::synlig_get_struct_member(buf);
                     if (id_ast->type == Yosys::AST::AST_WIRE && item_node) {
                         // The dimension of the original array expression is saved in the 'integer' field
                         dim += buf->integer;
@@ -4082,7 +4082,7 @@ replace_fcall_later:;
                             tmp_range_left = (param_width + 2 * param_offset) - ast_node->children[0]->range_right - 1;
                             tmp_range_right = (param_width + 2 * param_offset) - ast_node->children[0]->range_left - 1;
                         }
-                        Yosys::AST::AstNode *member_node = systemverilog_plugin::synlig_get_struct_member(ast_node);
+                        Yosys::AST::AstNode *member_node = Synlig::synlig_get_struct_member(ast_node);
                         int chunk_offset = member_node ? member_node->range_right : 0;
                         log_assert(!(chunk_offset && param_upto));
                         for (int i = tmp_range_right; i <= tmp_range_left; i++) {
@@ -4478,4 +4478,4 @@ replace_fcall_later:;
     return did_something;
 }
 
-} // namespace systemverilog_plugin
+} // namespace Synlig

src/mods/yosys_ast/synlig_simplify.h

@@ -1,9 +1,9 @@
 #include "frontends/ast/ast.h"
 
-namespace systemverilog_plugin
+namespace Synlig
 {
 using ys_size_type = int; // Makes it easy to change if changed upstream.
 bool synlig_simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint,
                      bool in_param);
 void synlig_expand_genblock(Yosys::AST::AstNode *current_node, std::string prefix, bool only_resolve_scope);
-} // namespace systemverilog_plugin
+} // namespace Synlig

tests/formal/README.md

@@ -40,7 +40,7 @@ A table below presents example for [results.py](results.py) script generated on
 |              FAIL | 23    | formally not equivalent                      |
 |              SKIP | 4     | not executed                                 |
 |   YOSYS_READ_FAIL | 58    | yosys couldn't read design                   |
-|  PLUGIN_READ_FAIL | 4     | synlig couldn't read design                  |
+|  SYNLIG_READ_FAIL | 4     | synlig couldn't read design                  |
 |      EMPTY_MODULE | 5     | synlig or yosys produced empty module        |
 |  UNMATCHED_MODULE | 13    | different module names or count was produced |
 |NOTHING_TO_COMPARE | 6     | there is nothing to compare in designs       |

tests/formal/results.py

@@ -12,7 +12,7 @@
     "FAIL":               "formally not equivalent",
     "SKIP":               "not executed",
     "YOSYS_READ_FAIL":    "yosys couldn't read design",
-    "PLUGIN_READ_FAIL":   "synlig couldn't read design",
+    "SYNLIG_READ_FAIL":   "synlig couldn't read design",
     "EMPTY_MODULE":       "synlig or yosys produced empty module",
     "UNMATCHED_MODULE":   "different module names or count was produced",
     "NOTHING_TO_COMPARE": "there is nothing to compare in designs",
@@ -70,7 +70,7 @@ def main():
             expected_result = performed_tests_summary[test]["expected_result"]
             performed_result = performed_tests_summary[test]["result"]
             if expected_result != performed_result:
-                if not (expected_result == "READ_FAIL" and performed_result in {"YOSYS_READ_FAIL", "PLUGIN_READ_FAIL"}):
+                if not (expected_result == "READ_FAIL" and performed_result in {"YOSYS_READ_FAIL", "SYNLIG_READ_FAIL"}):
                     results_different_then_expected.append((
                         test,
                         performed_result,