do not simulate in parsing tests

chipsalliance · Sep 27, 2023 · 44cf9c1 · 44cf9c1
1 parent 7d02457
commit 44cf9c1
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diff --git a/tests/simple_tests/InterfaceAlways/yosys_script.tcl b/tests/simple_tests/InterfaceAlways/yosys_script.tcl
@@ -3,4 +3,3 @@ source ../yosys_common.tcl
 prep -top \\top
 write_verilog
 write_verilog yosys.sv
-sim -rstlen 10 -vcd dump.vcd
diff --git a/tests/simple_tests/InterfaceAssign/yosys_script.tcl b/tests/simple_tests/InterfaceAssign/yosys_script.tcl
@@ -3,4 +3,3 @@ source ../yosys_common.tcl
 prep -top \\top
 write_verilog
 write_verilog yosys.sv
-sim -rstlen 10 -vcd dump.vcd
diff --git a/tests/simple_tests/InterfaceInitial/yosys_script.tcl b/tests/simple_tests/InterfaceInitial/yosys_script.tcl
@@ -3,4 +3,3 @@ source ../yosys_common.tcl
 prep -top \\top
 write_verilog
 write_verilog yosys.sv
-sim -rstlen 10 -vcd dump.vcd
diff --git a/tests/simple_tests/OneNetInterf/yosys_script.tcl b/tests/simple_tests/OneNetInterf/yosys_script.tcl
@@ -3,4 +3,3 @@ source ../yosys_common.tcl
 prep -top \\dut
 write_verilog
 write_verilog yosys.sv
-sim -clock i -rstlen 10 -vcd dump.vcd
diff --git a/tests/simple_tests/OneNetRange/yosys_script.tcl b/tests/simple_tests/OneNetRange/yosys_script.tcl
@@ -3,4 +3,3 @@ source ../yosys_common.tcl
 prep -top \\dut
 write_verilog
 write_verilog yosys.sv
-sim -clock i -rstlen 10 -vcd dump.vcd