Skip to content
main

Patch yosys-config to report accurate paths #5322

Sign in to view logs

Patch yosys-config to report accurate paths

Patch yosys-config to report accurate paths #5322

Triggered via pull request November 27, 2023 23:19
@aWZHY0yQH81uOYvHaWZHY0yQH81uOYvH
synchronize #2167
aWZHY0yQH81uOYvH:patch-yosys-config
Status Cancelled
Total duration 15m 8s
Artifacts 11

main.yml

on: pull_request
Matrix: build-binaries
Build sv2v
1m 25s
Build sv2v
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 21s
Style check
Test "Installation from source" from README
13m 33s
Test "Installation from source" from README
Upload GHA event file
8s
Upload GHA event file
Parsing Tests  /  SystemVerilog Plugin
4m 50s
Parsing Tests / SystemVerilog Plugin
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests  /  Ibex (Vivado synthesis)
4m 44s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
4m 49s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
4m 49s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
4m 49s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
4m 44s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
4m 44s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
4m 49s
Large Designs Tests / Black Parrot (ASIC synthesis)
Parsing Tests  /  Surelog
4m 50s
Parsing Tests / Surelog
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
4m 44s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Test With Packaged Yosys
1m 56s
Test With Packaged Yosys
Test With Bundled Yosys
1m 13s
Test With Bundled Yosys
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
0s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
0s
Parsing Tests / Summary Generation
Formal Verification Tests  /  Passlist Check
0s
Formal Verification Tests / Passlist Check
Release Package
0s
Release Package
Release Package Installation Test
0s
Release Package Installation Test
Fit to window
Zoom out
Zoom in

Annotations

16 errors and 4 warnings
Formal Verification Tests / sv2v
The operation was canceled.
Test "Installation from source" from README
The operation was canceled.
Formal Verification Tests / yosys
The operation was canceled.
Formal Verification Tests / simple
The operation was canceled.
Large Designs Tests / VeeR-EH1 (synthesis)
The operation was canceled.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
The operation was canceled.
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
The operation was canceled.
Large Designs Tests / Ibex (Vivado synthesis)
The operation was canceled.
Large Designs Tests / Opentitan parsing (quick)
The operation was canceled.
Large Designs Tests / Opentitan parsing (full/top-down)
The operation was canceled.
Large Designs Tests / Ibex (F4PGA synthesis)
The operation was canceled.
Large Designs Tests / Opentitan 9d82960888 (synthesis)
The operation was canceled.
Large Designs Tests / Black Parrot (ASIC synthesis)
The operation was canceled.
Large Designs Tests / Opentitan (synthesis)
The operation was canceled.
Parsing Tests / SystemVerilog Plugin
The operation was canceled.
Parsing Tests / Surelog
The operation was canceled.
Upload GHA event file
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/upload-artifact@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
Large Designs Tests / Opentitan parsing (quick)
No files were found with the provided path: **/plot_*.svg. No artifacts will be uploaded.
Large Designs Tests / Opentitan parsing (full/top-down)
No files were found with the provided path: **/plot_*.svg. No artifacts will be uploaded.
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: **/plot_*.svg. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
binaries Expired
126 MB
binaries-asan Expired
1.01 GB
binaries-debian Expired
126 MB
event.json Expired
35.8 KB
parsing_read-systemverilog_logs Expired
304 KB
parsing_read-systemverilog_yosys-sv Expired
9.42 KB
parsing_read-uhdm_logs Expired
440 KB
parsing_read-uhdm_yosys-sv Expired
15.9 KB
parsing_test-results Expired
1.02 KB
plots Expired
4 MB
sv2v Expired
8.3 MB