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Patch yosys-config to report accurate paths #5321

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Patch yosys-config to report accurate paths

Patch yosys-config to report accurate paths #5321

Triggered via pull request November 27, 2023 23:00
@aWZHY0yQH81uOYvHaWZHY0yQH81uOYvH
synchronize #2167
aWZHY0yQH81uOYvH:patch-yosys-config
Status Cancelled
Total duration 20m 0s
Artifacts 15

main.yml

on: pull_request
Matrix: build-binaries
Build sv2v
1m 33s
Build sv2v
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 28s
Style check
Test "Installation from source" from README
19m 8s
Test "Installation from source" from README
Upload GHA event file
3s
Upload GHA event file
Parsing Tests  /  SystemVerilog Plugin
11m 32s
Parsing Tests / SystemVerilog Plugin
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests  /  Ibex (Vivado synthesis)
6m 14s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
11m 10s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
11m 6s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
11m 6s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
6m 32s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
10m 59s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
11m 5s
Large Designs Tests / Black Parrot (ASIC synthesis)
Parsing Tests  /  Surelog
11m 45s
Parsing Tests / Surelog
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
9m 15s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Test With Packaged Yosys
1m 59s
Test With Packaged Yosys
Test With Bundled Yosys
1m 17s
Test With Bundled Yosys
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
0s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
0s
Parsing Tests / Summary Generation
Formal Verification Tests  /  Passlist Check
0s
Formal Verification Tests / Passlist Check
Release Package
0s
Release Package
Release Package Installation Test
0s
Release Package Installation Test
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Annotations

12 errors and 4 warnings
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
The operation was canceled.
Formal Verification Tests / simple
The operation was canceled.
Formal Verification Tests / sv2v
The operation was canceled.
Formal Verification Tests / yosys
The operation was canceled.
Test "Installation from source" from README
The operation was canceled.
Large Designs Tests / Black Parrot (ASIC synthesis)
The operation was canceled.
Large Designs Tests / Opentitan (synthesis)
The operation was canceled.
Large Designs Tests / Opentitan 9d82960888 (synthesis)
The operation was canceled.
Large Designs Tests / Ibex (F4PGA synthesis)
The operation was canceled.
Large Designs Tests / Opentitan parsing (full/top-down)
The operation was canceled.
Parsing Tests / SystemVerilog Plugin
The operation was canceled.
Parsing Tests / Surelog
The operation was canceled.
Upload GHA event file
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/upload-artifact@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: **/plot_*.svg. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
binaries Expired
126 MB
binaries-asan Expired
1.01 GB
binaries-debian Expired
126 MB
bsg-logs Expired
85.8 MB
bsg-outputs Expired
6.99 MB
event.json Expired
35.8 KB
lowrisc_ibex_top_artya7_surelog_0.1.bit Expired
2.09 MB
opentitan-logs-quick Expired
39.2 MB
parsing_read-systemverilog_logs Expired
3.55 MB
parsing_read-systemverilog_yosys-sv Expired
64.7 KB
parsing_read-uhdm_logs Expired
4.87 MB
parsing_read-uhdm_yosys-sv Expired
95.5 KB
parsing_test-results Expired
7.55 KB
plots Expired
7.68 MB
sv2v Expired
8.3 MB