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Struct hier path #5320

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Struct hier path

Struct hier path #5320

Triggered via pull request November 27, 2023 22:52
@alaindargelasalaindargelas
synchronize #2166
alaindargelas:struct_hier_path
Status Cancelled
Total duration 56m 41s
Artifacts 21

main.yml

on: pull_request
Matrix: build-binaries
Build sv2v
1m 21s
Build sv2v
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 20s
Style check
Test "Installation from source" from README
55m 47s
Test "Installation from source" from README
Upload GHA event file
3s
Upload GHA event file
Parsing Tests  /  SystemVerilog Plugin
29m 19s
Parsing Tests / SystemVerilog Plugin
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests  /  Ibex (Vivado synthesis)
6m 23s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
10m 47s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
41m 43s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
47m 44s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
6m 25s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
16m 42s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
47m 42s
Large Designs Tests / Black Parrot (ASIC synthesis)
Parsing Tests  /  Surelog
21m 41s
Parsing Tests / Surelog
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
9m 0s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Test With Packaged Yosys
1m 59s
Test With Packaged Yosys
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
0s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 6s
Parsing Tests / Summary Generation
Formal Verification Tests  /  Passlist Check
1m 3s
Formal Verification Tests / Passlist Check
Release Package
0s
Release Package
Release Package Installation Test
0s
Release Package Installation Test
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Annotations

3 errors and 3 warnings
Style check
Process completed with exit code 1.
Large Designs Tests / Black Parrot (ASIC synthesis)
The operation was canceled.
Large Designs Tests / Opentitan (synthesis)
The operation was canceled.
Upload GHA event file
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/upload-artifact@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.

Artifacts

Produced during runtime
Name Size
binaries Expired
126 MB
binaries-asan Expired
1.01 GB
binaries-debian Expired
126 MB
bp_e_bp_unicore_cfg.edif Expired
128 MB
bsg-logs Expired
85.8 MB
bsg-outputs Expired
6.99 MB
event.json Expired
27.5 KB
formal-verification-logs Expired
664 MB
formal-verification-tests-list Expired
53.5 KB
lowrisc_ibex_top_artya7_surelog_0.1.bit Expired
2.09 MB
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit Expired
9.28 MB
opentitan-logs-full Expired
165 MB
opentitan-logs-quick Expired
39.2 MB
parsing_read-systemverilog_logs Expired
14.7 MB
parsing_read-systemverilog_yosys-sv Expired
310 KB
parsing_read-uhdm_logs Expired
14.7 MB
parsing_read-uhdm_yosys-sv Expired
307 KB
parsing_test-results Expired
20.2 KB
plots Expired
19.4 MB
sv2v Expired
8.3 MB
top_artya7.bit Expired
2.09 MB