Patch yosys-config to report accurate paths
#5314
tgorochowikmain.yml
on: pull_request
Matrix: build-binaries
Build sv2v
1m 23s
Emit Workflow Info
0s
Style check
1m 20s
Test "Installation from source" from README
52m 4s
Upload GHA event file
3s
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests
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Ibex (Vivado synthesis)
6m 1s
Large Designs Tests
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Ibex (F4PGA synthesis)
10m 48s
Large Designs Tests
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Opentitan 9d82960888 (synthesis)
39m 59s
Large Designs Tests
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Opentitan (synthesis)
1h 15m
Large Designs Tests
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VeeR-EH1 (synthesis)
6m 11s
Large Designs Tests
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Black Parrot (AMD (Xilinx) FPGA synthesis)
22m 7s
Large Designs Tests
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Black Parrot (ASIC synthesis)
1h 4m
Diff generated BSG Micro Designs tests
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Parse and diff BSG Micro Designs
9m 20s
Test With Packaged Yosys
2m 3s
Matrix: Formal Verification Tests / tests-formal-verification
Release Package Installation Test
0s
Annotations
4 warnings
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Upload GHA event file
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/upload-artifact@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
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Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build
third_party/OpenROAD-flow-scripts/logs
third_party/OpenROAD-flow-scripts/reports
third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
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Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
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Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
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binaries
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binaries-asan
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binaries-debian
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126 MB |
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bp_e_bp_unicore_cfg.edif
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128 MB |
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bsg-logs
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85.8 MB |
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bsg-outputs
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6.99 MB |
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event.json
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32 KB |
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formal-verification-logs
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624 MB |
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formal-verification-tests-list
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lowrisc_ibex_top_artya7_surelog_0.1.bit
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lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif
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221 MB |
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lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
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9.28 MB |
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opentitan-logs-full
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165 MB |
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opentitan-logs-quick
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39.2 MB |
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parsing_read-systemverilog_logs
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14.7 MB |
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parsing_read-systemverilog_yosys-sv
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307 KB |
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parsing_read-uhdm_logs
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parsing_read-uhdm_yosys-sv
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304 KB |
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plots
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sv2v
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8.3 MB |
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top_artya7.bit
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2.09 MB |
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