Bump Yosys #5043

Job	Run time
Style check	1m 34s
Build Binaries	11m 39s
Emit Workflow Info	0s
Build Binaries (ASAN)	17m 50s
Build sv2v	1m 24s
Upload GHA event file	5s
Formal Verification Tests / simple	13m 40s
Large Designs Tests / Ibex (Vivado synthesis)	6m 29s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	0s
Formal Verification Tests / sv2v	18m 59s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 12s
Formal Verification Tests / yosys	17m 54s
Large Designs Tests / Opentitan (synthesis)	1h 57m 9s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	28m 0s
Large Designs Tests / Opentitan parsing (full/top-down)	2h 24m 24s
Large Designs Tests / VeeR-EH1 (synthesis)	6m 55s
Large Designs Tests / Opentitan parsing (quick)	1h 10m 14s
Large Designs Tests / Black Parrot (ASIC synthesis)	1h 31m 51s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	9m 10s
Parsing Tests / SystemVerilog Plugin	30m 12s
Parsing Tests / Surelog	21m 7s
Formal Verification Tests / Passlist Check	1m 6s
Parsing Tests / Summary Generation	1m 12s
Parsing Tests / Generate AST diff	4m 38s
Release Package	0s
Release Package Installation Test	0s
	10h 26m 44s

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