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Fix enum item redeclaration error on reimport #4921

Fix enum item redeclaration error on reimport

Fix enum item redeclaration error on reimport #4921

Triggered via pull request September 25, 2023 17:04
Status Cancelled
Total duration 1h 49m 48s
Artifacts 17
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main.yml

on: pull_request
Matrix: build-binaries
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 6s
Style check
Upload GHA event file
3s
Upload GHA event file
Parsing Tests  /  SystemVerilog Plugin
33m 23s
Parsing Tests / SystemVerilog Plugin
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests  /  Ibex (Vivado synthesis)
6m 23s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
11m 33s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
0s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
1h 38m
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
6m 16s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (synthesis)
7m 3s
Large Designs Tests / Black Parrot (synthesis)
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
9m 5s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
0s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 6s
Parsing Tests / Summary Generation
Formal Verification Tests  /  Passlist Check
1m 9s
Formal Verification Tests / Passlist Check
Release Package
0s
Release Package
Release Package Installation Test
0s
Release Package Installation Test
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7 errors and 3 warnings
Large Designs Tests / Black Parrot (synthesis)
Process completed with exit code 2.
Formal Verification Tests / simple
Process completed with exit code 3.
Formal Verification Tests / sv2v
Process completed with exit code 3.
Parsing Tests / Surelog
Process completed with exit code 1.
Parsing Tests / SystemVerilog Plugin
Process completed with exit code 1.
Large Designs Tests / Opentitan (synthesis)
The operation was canceled.
Large Designs Tests / Opentitan parsing (full/top-down)
The operation was canceled.
Upload GHA event file
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/upload-artifact@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.

Artifacts

Produced during runtime
Name Size
binaries Expired
205 MB
binaries-asan Expired
1.3 GB
bsg-logs Expired
80.9 MB
bsg-outputs Expired
6.99 MB
event.json Expired
27.9 KB
formal-verification-logs Expired
645 MB
formal-verification-tests-list Expired
53.2 KB
lowrisc_ibex_top_artya7_surelog_0.1.bit Expired
2.09 MB
opentitan-logs-quick Expired
39.6 MB
parsing_read-systemverilog_logs Expired
14.3 MB
parsing_read-systemverilog_yosys-sv Expired
320 KB
parsing_read-uhdm_logs Expired
14.2 MB
parsing_read-uhdm_yosys-sv Expired
318 KB
parsing_test-results Expired
19.8 KB
plots Expired
23.2 MB
sv2v Expired
8.3 MB
top_artya7.bit Expired
2.09 MB