Fix enum item redeclaration error on reimport #4921
Triggered via pull request
September 25, 2023 17:04
Status
Cancelled
Total duration
1h 49m 48s
Artifacts
17
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main.yml
on: pull_request
Matrix: build-binaries
Build sv2v
1m 28s
Emit Workflow Info
0s
Style check
1m 6s
Upload GHA event file
3s
Matrix: Large Designs Tests / opentitan_parse_report
Large Designs Tests
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Ibex (Vivado synthesis)
6m 23s
Large Designs Tests
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Ibex (F4PGA synthesis)
11m 33s
Large Designs Tests
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Opentitan 9d82960888 (synthesis)
0s
Large Designs Tests
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Opentitan (synthesis)
1h 38m
Large Designs Tests
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VeeR-EH1 (synthesis)
6m 16s
Large Designs Tests
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Black Parrot (synthesis)
7m 3s
Diff generated BSG Micro Designs tests
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Parse and diff BSG Micro Designs
9m 5s
Matrix: Formal Verification Tests / tests-formal-verification
Release Package Installation Test
0s
Annotations
7 errors and 3 warnings
Large Designs Tests / Black Parrot (synthesis)
Process completed with exit code 2.
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Formal Verification Tests / simple
Process completed with exit code 3.
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Formal Verification Tests / sv2v
Process completed with exit code 3.
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Parsing Tests / Surelog
Process completed with exit code 1.
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Parsing Tests / SystemVerilog Plugin
Process completed with exit code 1.
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Large Designs Tests / Opentitan (synthesis)
The operation was canceled.
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Large Designs Tests / Opentitan parsing (full/top-down)
The operation was canceled.
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Upload GHA event file
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/upload-artifact@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
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Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
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Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
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Artifacts
Produced during runtime
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binaries
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205 MB |
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binaries-asan
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1.3 GB |
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bsg-logs
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80.9 MB |
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bsg-outputs
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6.99 MB |
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event.json
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27.9 KB |
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formal-verification-logs
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645 MB |
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formal-verification-tests-list
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53.2 KB |
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lowrisc_ibex_top_artya7_surelog_0.1.bit
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2.09 MB |
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opentitan-logs-quick
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39.6 MB |
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parsing_read-systemverilog_logs
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14.3 MB |
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parsing_read-systemverilog_yosys-sv
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320 KB |
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parsing_read-uhdm_logs
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14.2 MB |
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parsing_read-uhdm_yosys-sv
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318 KB |
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parsing_test-results
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19.8 KB |
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plots
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23.2 MB |
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sv2v
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8.3 MB |
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top_artya7.bit
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2.09 MB |
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