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update surelog const propagation #4914

Job	Run time
Build sv2v	1m 55s
Build Binaries	4m 18s
Build Binaries (ASAN)	8m 32s
Emit Workflow Info	0s
Style check	1m 11s
Upload GHA event file	2s
Large Designs Tests / Ibex (Vivado synthesis)	6m 19s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	9m 30s
Formal Verification Tests / simple	13m 15s
Large Designs Tests / Black Parrot (synthesis)	35m 25s
Formal Verification Tests / sv2v	17m 45s
Formal Verification Tests / yosys	18m 8s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 33s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	0s
Large Designs Tests / Opentitan parsing (full/top-down)	2h 28m 27s
Large Designs Tests / Opentitan parsing (quick)	1h 8m 55s
Large Designs Tests / VeeR-EH1 (synthesis)	6m 2s
Parsing Tests / SystemVerilog Plugin	30m 4s
Large Designs Tests / Opentitan (synthesis)	1h 49m 17s
Parsing Tests / Surelog	21m 12s
Formal Verification Tests / Passlist Check	1m 10s
Parsing Tests / Summary Generation	1m 4s
Parsing Tests / Generate AST diff	0s
Release Package	0s
Release Package Installation Test	0s
	8h 34m 4s

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