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wsip/bump_yosys #4899

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Manually triggered September 21, 2023 13:38

wsipak

wsip/bump_yosys

Status Failure

Total duration 2h 47m 52s

Artifacts 19

This run and associated checks have been archived and are scheduled for deletion. Learn more about checks retention

main.yml

on: workflow_dispatch

Matrix: build-binaries

Emit Workflow Info

Upload GHA event file

Parsing Tests / SystemVerilog Plugin

Matrix: Large Designs Tests / opentitan_parse_report

Large Designs Tests / Ibex (Vivado synthesis)

Large Designs Tests / Ibex (F4PGA synthesis)

Large Designs Tests / Opentitan 9d82960888 (synthesis)

Large Designs Tests / Opentitan (synthesis)

Large Designs Tests / VeeR-EH1 (synthesis)

Large Designs Tests / Black Parrot (synthesis)

Parsing Tests / Surelog

Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs

Matrix: Formal Verification Tests / tests-formal-verification

Parsing Tests / Generate AST diff

Parsing Tests / Summary Generation

Formal Verification Tests / Passlist Check

Release Package

Release Package Installation Test

Annotations

6 errors and 3 warnings

Large Designs Tests / Ibex (Vivado synthesis)

Process completed with exit code 2.

Formal Verification Tests / simple

Process completed with exit code 2.

Formal Verification Tests / yosys

Process completed with exit code 2.

Formal Verification Tests / sv2v

Process completed with exit code 3.

Parsing Tests / Surelog

Process completed with exit code 1.

Parsing Tests / SystemVerilog Plugin

Process completed with exit code 1.

Upload GHA event file

The following actions uses node12 which is deprecated and will be forced to run on node16: actions/upload-artifact@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/

Large Designs Tests / VeeR-EH1 (synthesis)

No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.

Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs

Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.

Artifacts

Produced during runtime

Name	Size
binaries Expired	205 MB
binaries-asan Expired	1.31 GB
bp_e_bp_unicore_cfg.edif Expired	119 MB
bsg-logs Expired	80.9 MB
bsg-outputs Expired	7 MB
event.json Expired	7.63 KB
formal-verification-logs Expired	627 MB
formal-verification-tests-list Expired	53.4 KB
lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif Expired	259 MB
opentitan-logs-full Expired	166 MB
opentitan-logs-quick Expired	39.6 MB
parsing_read-systemverilog_logs Expired	14.4 MB
parsing_read-systemverilog_yosys-sv Expired	324 KB
parsing_read-uhdm_logs Expired	14.2 MB
parsing_read-uhdm_yosys-sv Expired	322 KB
parsing_test-results Expired	19.7 KB
plots Expired	31 MB
sv2v Expired	8.3 MB
top_artya7.bit Expired	2.09 MB