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Build(deps): Bump third_party/ibex from `87dfd07` to `a05d4d8` #6105

Job	Run time
Build tools	10m 49s
Build Synlig Release	4m 48s
Emit Workflow Info	0s
Build Plugin	4m 4s
Build Synlig (ASAN)	7m 54s
Style check	1m 30s
Build Package	4m 32s
Verify README Correctness (Installation From Sources)	43m 13s
Build PySynlig	10m 1s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	14m 35s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 42s
Large Designs Tests / Black Parrot (ASIC synthesis)	40m 53s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	40m 8s
Large Designs Tests / Ibex (Vivado synthesis)	3m 1s
Large Designs Tests / Ibex (F4PGA synthesis)	5m 41s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	30m 18s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 4s
Large Designs Tests / Opentitan (synthesis)	47m 38s
Large Designs Tests / Opentitan parsing (quick)	5m 12s
Parsing Tests / Test read_systemverilog release	4m 53s
Parsing Tests / Test read_uhdm release	4m 22s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 29s
Parsing Tests / Test read_systemverilog plugin	4m 53s
Parsing Tests / Test read_uhdm plugin	4m 26s
Parsing Tests / Test read_systemverilog asan	35m 38s
Parsing Tests / Test read_uhdm asan	25m 22s
Formal Verification Tests / simple	17m 6s
Formal Verification Tests / sv2v	17m 34s
Formal Verification Tests / yosys	14m 24s
Parsing Tests / Summary Generation	1m 45s
Parsing Tests / Generate AST diff	1m 47s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	7h 10m 42s

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