Build(deps): Bump third_party/sv2v from `e9c01d2` to `aa0a885` #6101

Job	Run time
Build Synlig Release	4m 21s
Build Plugin	3m 50s
Build tools	11m 28s
Build Synlig (ASAN)	7m 0s
Build Package	4m 22s
Emit Workflow Info	0s
Build PySynlig	8m 35s
Style check	1m 38s
Verify README Correctness (Installation From Sources)	41m 34s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	39m 25s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	16m 51s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 20s
Large Designs Tests / Black Parrot (ASIC synthesis)	40m 40s
Large Designs Tests / Ibex (Vivado synthesis)	6m 43s
Large Designs Tests / Ibex (F4PGA synthesis)	12m 0s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	31m 50s
Large Designs Tests / Opentitan parsing (full/top-down)	13m 43s
Large Designs Tests / Opentitan parsing (quick)	5m 29s
Large Designs Tests / Opentitan (synthesis)	57m 3s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 32s
Parsing Tests / Test read_systemverilog release	4m 33s
Parsing Tests / Test read_uhdm release	4m 20s
Parsing Tests / Test read_systemverilog plugin	4m 44s
Parsing Tests / Test read_uhdm plugin	4m 23s
Parsing Tests / Test read_systemverilog asan	36m 48s
Parsing Tests / Test read_uhdm asan	25m 38s
Formal Verification Tests / simple	17m 13s
Formal Verification Tests / sv2v	18m 2s
Formal Verification Tests / yosys	14m 44s
Parsing Tests / Summary Generation	1m 30s
Parsing Tests / Generate AST diff	1m 52s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	7h 32m 11s

Provide feedback