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Build(deps): Bump third_party/surelog from `5120036` to `298a9cd` (#2… #6095

Job	Run time
Build Synlig Release	21m 18s
Build Plugin	20m 42s
Build Synlig (ASAN)	21m 28s
Build Package	20m 57s
Build PySynlig	26m 15s
Build tools	10m 49s
Emit Workflow Info	0s
Style check	1m 35s
Verify README Correctness (Installation From Sources)	42m 13s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 33s
Formal Verification Tests / simple	17m 29s
Large Designs Tests / Ibex (Vivado synthesis)	6m 24s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 20s
Formal Verification Tests / sv2v	17m 20s
Formal Verification Tests / yosys	14m 45s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	33m 7s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 49s
Large Designs Tests / Opentitan (synthesis)	47m 31s
Large Designs Tests / Opentitan parsing (quick)	5m 0s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 22s
Large Designs Tests / Black Parrot (ASIC synthesis)	45m 1s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	15m 42s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	40m 30s
Parsing Tests / Test read_systemverilog release	4m 24s
Parsing Tests / Test read_uhdm release	4m 9s
Parsing Tests / Test read_systemverilog plugin	4m 34s
Parsing Tests / Test read_uhdm plugin	4m 9s
Parsing Tests / Test read_systemverilog asan	35m 14s
Parsing Tests / Test read_uhdm asan	25m 20s
Parsing Tests / Summary Generation	1m 31s
Parsing Tests / Generate AST diff	1m 36s
Release Package	17s
Verify README Correctness (Download And Run Release)	1m 47s
	8h 47m 11s

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