Build(deps): Bump third_party/ibex from `87dfd07` to `667fd20` #6092

Job	Run time
Build Synlig Release	17m 7s
Build Plugin	17m 43s
Emit Workflow Info	0s
Build Synlig (ASAN)	7m 0s
Build Package	18m 10s
Build PySynlig	21m 14s
Style check	1m 26s
Build tools	10m 32s
Verify README Correctness (Installation From Sources)	43m 8s
Formal Verification Tests / simple	17m 36s
Large Designs Tests / Ibex (Vivado synthesis)	2m 38s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 36s
Formal Verification Tests / sv2v	17m 5s
Large Designs Tests / Ibex (F4PGA synthesis)	5m 36s
Formal Verification Tests / yosys	14m 27s
Large Designs Tests / Black Parrot (ASIC synthesis)	39m 23s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	42m 26s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	14m 49s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	33m 47s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 12s
Large Designs Tests / Opentitan (synthesis)	58m 19s
Large Designs Tests / Opentitan parsing (full/top-down)	11m 57s
Parsing Tests / Test read_systemverilog release	4m 20s
Large Designs Tests / Opentitan parsing (quick)	4m 58s
Parsing Tests / Test read_uhdm release	4m 25s
Parsing Tests / Test read_systemverilog plugin	4m 32s
Parsing Tests / Test read_uhdm plugin	4m 14s
Parsing Tests / Test read_systemverilog asan	35m 30s
Parsing Tests / Test read_uhdm asan	25m 13s
Parsing Tests / Summary Generation	1m 30s
Parsing Tests / Generate AST diff	1m 46s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	8h 12m 39s

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