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Build(deps): Bump third_party/ibex from 87dfd07 to 0945aa8 #6085

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Build(deps): Bump third_party/ibex from 87dfd07 to 0945aa8

Build(deps): Bump third_party/ibex from 87dfd07 to 0945aa8 #6085

Triggered via pull request December 4, 2024 07:20
@dependabotdependabot[bot]
opened #2693
dependabot/submodules/third_party/ibex-0945aa8
Status Failure
Total duration 1h 19m 11s
Artifacts 47

main.yml

on: pull_request
Matrix: build-binaries
Build tools
10m 37s
Build tools
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 37s
Style check
Verify README Correctness (Installation From Sources)
41m 57s
Verify README Correctness (Installation From Sources)
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests  /  Ibex (Vivado synthesis)
2m 38s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
5m 16s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
24m 29s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
53m 42s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
5m 12s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
16m 23s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
39m 39s
Large Designs Tests / Black Parrot (ASIC synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) with PySynlig)
33m 38s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
6m 20s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
1m 55s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 51s
Parsing Tests / Summary Generation
Release Package
0s
Release Package
Verify README Correctness (Download And Run Release)
0s
Verify README Correctness (Download And Run Release)
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Annotations

2 errors and 4 warnings
Large Designs Tests / Ibex (Vivado synthesis)
Process completed with exit code 2.
Large Designs Tests / Ibex (F4PGA synthesis)
Process completed with exit code 2.
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build third_party/OpenROAD-flow-scripts/logs third_party/OpenROAD-flow-scripts/reports third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
binaries-asan
292 MB
binaries-package
23.2 MB
binaries-plugin
41.7 MB
binaries-pysynlig
651 MB
binaries-release
42 MB
bp_e_bp_unicore_cfg.edif
3.92 MB
bsg-logs
5.57 MB
bsg-outputs
1.73 MB
formal-verification-logs-simple
18.7 MB
formal-verification-logs-sv2v
62.6 MB
formal-verification-logs-yosys
50.1 MB
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
616 KB
opentitan-logs-full
4.58 MB
opentitan-logs-quick
831 KB
plots_binaries-asan
52.8 KB
plots_binaries-package
145 KB
plots_binaries-plugin
147 KB
plots_binaries-pysynlig
168 KB
plots_binaries-release
142 KB
plots_blackparrot_synth_asic
236 KB
plots_blackparrot_synth_xilinx
107 KB
plots_blackparrot_synth_xilinx_python
194 KB
plots_build_tools
79.5 KB
plots_formal_verification_simple
115 KB
plots_formal_verification_sv2v
117 KB
plots_formal_verification_yosys
95.4 KB
plots_ibex_synth
19.2 KB
plots_ibex_synth_f4pga
40.9 KB
plots_opentitan_9d82960888_synth
142 KB
plots_opentitan_parse_report_full
78.2 KB
plots_opentitan_parse_report_quick
37.6 KB
plots_opentitan_synth
288 KB
plots_tests_asan_read_systemverilog
221 KB
plots_tests_asan_read_uhdm
167 KB
plots_tests_plugin_read_systemverilog
34.9 KB
plots_tests_plugin_read_uhdm
35.7 KB
plots_tests_release_read_systemverilog
34.5 KB
plots_tests_release_read_uhdm
32.7 KB
plots_veer_synth
35.9 KB
python_bp_e_bp_unicore_cfg.edif
3.92 MB
results_parsing_tests_asan_read_systemverilog Expired
1.6 MB
results_parsing_tests_asan_read_uhdm Expired
1.81 MB
results_parsing_tests_plugin_read_systemverilog Expired
1.53 MB
results_parsing_tests_plugin_read_uhdm Expired
1.78 MB
results_parsing_tests_release_read_systemverilog Expired
1.48 MB
results_parsing_tests_release_read_uhdm Expired
1.73 MB
tools
39.2 MB