main

Build(deps): Bump third_party/yosys from `6f3376c` to `889894a` #6084

Job	Run time
Emit Workflow Info	0s
Build Synlig Release	22m 1s
Build tools	11m 22s
Build Plugin	16m 35s
Build Synlig (ASAN)	7m 58s
Style check	1m 28s
Build Package	21m 52s
Verify README Correctness (Installation From Sources)	41m 43s
Build PySynlig	21m 19s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 29s
Large Designs Tests / Black Parrot (ASIC synthesis)	34m 57s
Formal Verification Tests / simple	17m 17s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	13m 31s
Formal Verification Tests / sv2v	17m 15s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	30m 27s
Formal Verification Tests / yosys	14m 54s
Large Designs Tests / Ibex (Vivado synthesis)	6m 21s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 21s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	24m 58s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 0s
Large Designs Tests / Opentitan parsing (quick)	5m 2s
Large Designs Tests / Opentitan (synthesis)	48m 23s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 12s
Parsing Tests / Test read_systemverilog release	4m 30s
Parsing Tests / Test read_uhdm release	4m 23s
Parsing Tests / Test read_systemverilog plugin	4m 34s
Parsing Tests / Test read_uhdm plugin	4m 24s
Parsing Tests / Test read_systemverilog asan	36m 11s
Parsing Tests / Test read_uhdm asan	25m 12s
Parsing Tests / Summary Generation	1m 27s
Parsing Tests / Generate AST diff	1m 40s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	7h 54m 46s

Provide feedback