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Build(deps): Bump third_party/yosys from `6f3376c` to `f04b899` #6083

Job	Run time
Build Synlig Release	4m 36s
Build tools	10m 42s
Build Plugin	3m 55s
Build Synlig (ASAN)	6m 59s
Build Package	4m 36s
Emit Workflow Info	0s
Build PySynlig	10m 44s
Verify README Correctness (Installation From Sources)	42m 17s
Style check	1m 45s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 41s
Formal Verification Tests / simple	16m 47s
Parsing Tests / Test read_systemverilog release	5m 20s
Formal Verification Tests / sv2v	15m 1s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	23m 22s
Parsing Tests / Test read_uhdm release	4m 54s
Formal Verification Tests / yosys	13m 19s
Parsing Tests / Test read_systemverilog plugin	4m 53s
Parsing Tests / Test read_uhdm plugin	4m 51s
Large Designs Tests / Opentitan (synthesis)	51m 24s
Parsing Tests / Test read_systemverilog asan	36m 12s
Large Designs Tests / Ibex (Vivado synthesis)	6m 38s
Parsing Tests / Test read_uhdm asan	25m 52s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 44s
Large Designs Tests / Black Parrot (ASIC synthesis)	29m 53s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	11m 36s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 2s
Large Designs Tests / Opentitan parsing (quick)	5m 11s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 21s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	32m 42s
Parsing Tests / Summary Generation	9m 1s
Parsing Tests / Generate AST diff	3m 8s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	7h 1m 26s

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