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Add alias for write_rtlil only when ilang frontend doesn't exist (#2685) #6078

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Triggered via push November 28, 2024 11:15

main

Status Cancelled

Total duration 48m 21s

Artifacts 49

main.yml

on: push

Matrix: build-binaries

Emit Workflow Info

Verify README Correctness (Installation From Sources)

Matrix: Large Designs Tests / opentitan_parse_report

Matrix: Parsing Tests / parsing-tests

Large Designs Tests / Ibex (Vivado synthesis)

Large Designs Tests / Ibex (F4PGA synthesis)

Large Designs Tests / Opentitan 9d82960888 (synthesis)

Large Designs Tests / Opentitan (synthesis)

Large Designs Tests / VeeR-EH1 (synthesis)

Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)

Large Designs Tests / Black Parrot (ASIC synthesis)

Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)

Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs

Matrix: Formal Verification Tests / tests-formal-verification

Parsing Tests / Generate AST diff

Parsing Tests / Summary Generation

Release Package

Verify README Correctness (Download And Run Release)

Annotations

10 errors and 2 warnings

Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)

Canceling since a higher priority waiting request for 'chipsalliance/synlig-main-refs/heads/main' exists

Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)

The operation was canceled.

Parsing Tests / Summary Generation

Canceling since a higher priority waiting request for 'chipsalliance/synlig-main-refs/heads/main' exists

Parsing Tests / Summary Generation

The operation was canceled.

Parsing Tests / Generate AST diff

Canceling since a higher priority waiting request for 'chipsalliance/synlig-main-refs/heads/main' exists

Parsing Tests / Generate AST diff

The operation was canceled.

Large Designs Tests / Black Parrot (ASIC synthesis)

Canceling since a higher priority waiting request for 'chipsalliance/synlig-main-refs/heads/main' exists

Large Designs Tests / Black Parrot (ASIC synthesis)

The operation was canceled.

Large Designs Tests / Opentitan (synthesis)

Canceling since a higher priority waiting request for 'chipsalliance/synlig-main-refs/heads/main' exists

Large Designs Tests / Opentitan (synthesis)

The operation was canceled.

Large Designs Tests / VeeR-EH1 (synthesis)

No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.

Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs

Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.

Artifacts

Produced during runtime

Name	Size
binaries-asan	292 MB
binaries-package	23.2 MB
binaries-plugin	41.7 MB
binaries-pysynlig	651 MB
binaries-release	42 MB
bp_e_bp_unicore_cfg.edif	3.92 MB
bsg-logs	5.57 MB
bsg-outputs	1.73 MB
formal-verification-logs-simple	18.5 MB
formal-verification-logs-sv2v	62.6 MB
formal-verification-logs-yosys	50.1 MB
lowrisc_ibex_top_artya7_surelog_0.1.bit	105 KB
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit	616 KB
opentitan-logs-full	4.55 MB
opentitan-logs-quick	829 KB
opentitan-synlig.ast	134 MB
plots_binaries-asan	53.5 KB
plots_binaries-package	31.8 KB
plots_binaries-plugin	30.1 KB
plots_binaries-pysynlig	64.1 KB
plots_binaries-release	32.3 KB
plots_blackparrot_synth_asic	202 KB
plots_blackparrot_synth_xilinx	105 KB
plots_blackparrot_synth_xilinx_python	194 KB
plots_build_tools	79.6 KB
plots_formal_verification_simple	98.3 KB
plots_formal_verification_sv2v	95.4 KB
plots_formal_verification_yosys	81 KB
plots_ibex_synth	45.3 KB
plots_ibex_synth_f4pga	79.8 KB
plots_opentitan_9d82960888_synth	186 KB
plots_opentitan_parse_report_full	99.5 KB
plots_opentitan_parse_report_quick	47.3 KB
plots_opentitan_synth	199 KB
plots_tests_asan_read_systemverilog	223 KB
plots_tests_asan_read_uhdm	165 KB
plots_tests_plugin_read_systemverilog	35.5 KB
plots_tests_plugin_read_uhdm	32.6 KB
plots_tests_release_read_systemverilog	35 KB
plots_tests_release_read_uhdm	32.7 KB
plots_veer_synth	37.6 KB
results_parsing_tests_asan_read_systemverilog Expired	1.6 MB
results_parsing_tests_asan_read_uhdm Expired	1.81 MB
results_parsing_tests_plugin_read_systemverilog Expired	1.53 MB
results_parsing_tests_plugin_read_uhdm Expired	1.78 MB
results_parsing_tests_release_read_systemverilog Expired	1.49 MB
results_parsing_tests_release_read_uhdm Expired	1.73 MB
tools	39.2 MB
top_artya7.bit	119 KB