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Update outdated naming #6074

Job	Run time
Build tools	10m 54s
Style check	1m 33s
Build Synlig Release	5m 16s
Build Plugin	4m 50s
Build Synlig (ASAN)	8m 23s
Emit Workflow Info	0s
Verify README Correctness (Installation From Sources)	43m 45s
Build Package	5m 23s
Build PySynlig	10m 48s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 28s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	15m 14s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	39m 9s
Large Designs Tests / Black Parrot (ASIC synthesis)	44m 6s
Large Designs Tests / Ibex (Vivado synthesis)	6m 30s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 11s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	34m 15s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 12s
Large Designs Tests / Opentitan parsing (quick)	4m 58s
Large Designs Tests / Opentitan (synthesis)	53m 5s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 16s
Parsing Tests / Test read_systemverilog release	4m 19s
Parsing Tests / Test read_uhdm release	4m 8s
Parsing Tests / Test read_systemverilog plugin	4m 48s
Parsing Tests / Test read_uhdm plugin	4m 16s
Parsing Tests / Test read_systemverilog asan	34m 46s
Parsing Tests / Test read_uhdm asan	25m 38s
Formal Verification Tests / simple	17m 47s
Formal Verification Tests / sv2v	16m 58s
Formal Verification Tests / yosys	14m 21s
Parsing Tests / Generate AST diff	1m 41s
Parsing Tests / Summary Generation	2m 7s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	7h 34m 5s

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