Build(deps): Bump third_party/yosys from `98b4aff` to `6f3376c` #6072

Job	Run time
Verify README Correctness (Installation From Sources)	42m 20s
Style check	1m 30s
Build Synlig Release	12m 53s
Build Plugin	13m 36s
Build tools	10m 32s
Build Synlig (ASAN)	15m 46s
Emit Workflow Info	0s
Build Package	13m 10s
Build PySynlig	19m 44s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 31s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	32m 10s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	16m 34s
Large Designs Tests / Black Parrot (ASIC synthesis)	41m 28s
Large Designs Tests / Ibex (Vivado synthesis)	6m 21s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 23s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	25m 10s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 24s
Large Designs Tests / Opentitan (synthesis)	50m 12s
Large Designs Tests / Opentitan parsing (quick)	4m 58s
Formal Verification Tests / simple	14m 55s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 26s
Formal Verification Tests / sv2v	15m 11s
Parsing Tests / Test read_systemverilog release	4m 30s
Parsing Tests / Test read_uhdm release	4m 17s
Formal Verification Tests / yosys	12m 42s
Parsing Tests / Test read_systemverilog plugin	4m 31s
Parsing Tests / Test read_uhdm plugin	4m 26s
Parsing Tests / Test read_systemverilog asan	35m 25s
Parsing Tests / Test read_uhdm asan	26m 15s
Parsing Tests / Summary Generation	1m 51s
Parsing Tests / Generate AST diff	1m 50s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	7h 48m 1s

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