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Build(deps): Bump third_party/yosys from b89bd02 to 98b4aff (#2681) #6069

Build(deps): Bump third_party/yosys from b89bd02 to 98b4aff (#2681)

Build(deps): Bump third_party/yosys from b89bd02 to 98b4aff (#2681) #6069

Triggered via push November 26, 2024 08:23
Status Success
Total duration 1h 12m 54s
Artifacts 50

main.yml

on: push
Matrix: build-binaries
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 51s
Style check
Verify README Correctness (Installation From Sources)
41m 32s
Verify README Correctness (Installation From Sources)
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests  /  Ibex (Vivado synthesis)
6m 10s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
11m 27s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
33m 27s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
59m 51s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
5m 17s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
16m 32s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
39m 8s
Large Designs Tests / Black Parrot (ASIC synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) with PySynlig)
39m 31s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
6m 32s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
1m 46s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 33s
Parsing Tests / Summary Generation
Release Package
11s
Release Package
Verify README Correctness (Download And Run Release)
2m 15s
Verify README Correctness (Download And Run Release)
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Annotations

4 warnings
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build third_party/OpenROAD-flow-scripts/logs third_party/OpenROAD-flow-scripts/reports third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
binaries-asan
292 MB
binaries-package
23.2 MB
binaries-plugin
41.7 MB
binaries-pysynlig
651 MB
binaries-release
42 MB
bp_e_bp_unicore_cfg.edif
3.92 MB
bsg-logs
5.57 MB
bsg-outputs
1.73 MB
formal-verification-logs-simple
18.7 MB
formal-verification-logs-sv2v
62.6 MB
formal-verification-logs-yosys
50.2 MB
lowrisc_ibex_top_artya7_surelog_0.1.bit
105 KB
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
616 KB
opentitan-logs-full
4.56 MB
opentitan-logs-quick
828 KB
opentitan-synlig.ast
134 MB
plots_binaries-asan
55.3 KB
plots_binaries-package
32.6 KB
plots_binaries-plugin
30.4 KB
plots_binaries-pysynlig
66 KB
plots_binaries-release
33 KB
plots_blackparrot_synth_asic
233 KB
plots_blackparrot_synth_xilinx
107 KB
plots_blackparrot_synth_xilinx_python
230 KB
plots_build_tools
78.9 KB
plots_formal_verification_simple
112 KB
plots_formal_verification_sv2v
114 KB
plots_formal_verification_yosys
97.4 KB
plots_ibex_synth
45.1 KB
plots_ibex_synth_f4pga
82.3 KB
plots_opentitan_9d82960888_synth
189 KB
plots_opentitan_parse_report_full
80 KB
plots_opentitan_parse_report_quick
38.8 KB
plots_opentitan_synth
311 KB
plots_tests_asan_read_systemverilog
222 KB
plots_tests_asan_read_uhdm
160 KB
plots_tests_plugin_read_systemverilog
39.3 KB
plots_tests_plugin_read_uhdm
34.3 KB
plots_tests_release_read_systemverilog
35.1 KB
plots_tests_release_read_uhdm
33.4 KB
plots_veer_synth
35.5 KB
python_bp_e_bp_unicore_cfg.edif
3.92 MB
results_parsing_tests_asan_read_systemverilog Expired
1.6 MB
results_parsing_tests_asan_read_uhdm Expired
1.81 MB
results_parsing_tests_plugin_read_systemverilog Expired
1.53 MB
results_parsing_tests_plugin_read_uhdm Expired
1.78 MB
results_parsing_tests_release_read_systemverilog Expired
1.49 MB
results_parsing_tests_release_read_uhdm Expired
1.73 MB
tools
39.2 MB
top_artya7.bit
119 KB