Build(deps): Bump third_party/black_parrot from 65c7db6 to d28efc7
#6067
dependabot[bot]main.yml
on: pull_request
Matrix: build-binaries
Build tools
10m 37s
Emit Workflow Info
0s
Style check
1m 38s
Verify README Correctness (Installation From Sources)
43m 11s
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests
/
Ibex (Vivado synthesis)
6m 57s
Large Designs Tests
/
Ibex (F4PGA synthesis)
12m 14s
Large Designs Tests
/
Opentitan 9d82960888 (synthesis)
31m 44s
Large Designs Tests
/
Opentitan (synthesis)
1h 1m
Large Designs Tests
/
VeeR-EH1 (synthesis)
5m 57s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) FPGA synthesis)
3m 15s
Large Designs Tests
/
Black Parrot (ASIC synthesis)
3m 57s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) with PySynlig)
4m 39s
Diff generated BSG Micro Designs tests
/
Parse and diff BSG Micro Designs
6m 50s
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests
/
Generate AST diff
2m 11s
Parsing Tests
/
Summary Generation
1m 37s
Verify README Correctness (Download And Run Release)
0s
Annotations
3 errors and 3 warnings
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Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Process completed with exit code 2.
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Large Designs Tests / Black Parrot (ASIC synthesis)
Process completed with exit code 2.
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Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Process completed with exit code 2.
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Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
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Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
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Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.
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Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
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binaries-asan
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291 MB |
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binaries-package
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23.2 MB |
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binaries-plugin
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41.7 MB |
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binaries-pysynlig
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651 MB |
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binaries-release
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41.9 MB |
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bsg-logs
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5.57 MB |
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bsg-outputs
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1.73 MB |
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formal-verification-logs-simple
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18.6 MB |
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formal-verification-logs-sv2v
|
62.7 MB |
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formal-verification-logs-yosys
|
50.3 MB |
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lowrisc_ibex_top_artya7_surelog_0.1.bit
|
105 KB |
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lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
|
616 KB |
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opentitan-logs-full
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4.59 MB |
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opentitan-logs-quick
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827 KB |
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plots_binaries-asan
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53.9 KB |
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plots_binaries-package
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31.7 KB |
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plots_binaries-plugin
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30.3 KB |
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plots_binaries-pysynlig
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67.9 KB |
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plots_binaries-release
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31.4 KB |
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plots_blackparrot_synth_asic
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27.8 KB |
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plots_blackparrot_synth_xilinx
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23.5 KB |
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plots_blackparrot_synth_xilinx_python
|
30.5 KB |
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plots_build_tools
|
78.2 KB |
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plots_formal_verification_simple
|
113 KB |
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plots_formal_verification_sv2v
|
116 KB |
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plots_formal_verification_yosys
|
96.1 KB |
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plots_ibex_synth
|
47.2 KB |
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plots_ibex_synth_f4pga
|
83.9 KB |
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plots_opentitan_9d82960888_synth
|
175 KB |
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plots_opentitan_parse_report_full
|
82.2 KB |
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plots_opentitan_parse_report_quick
|
37.5 KB |
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plots_opentitan_synth
|
301 KB |
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plots_tests_asan_read_systemverilog
|
226 KB |
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plots_tests_asan_read_uhdm
|
169 KB |
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plots_tests_plugin_read_systemverilog
|
36.3 KB |
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plots_tests_plugin_read_uhdm
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33.8 KB |
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plots_tests_release_read_systemverilog
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35 KB |
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plots_tests_release_read_uhdm
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34.5 KB |
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plots_veer_synth
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40.5 KB |
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results_parsing_tests_asan_read_systemverilog
Expired
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1.6 MB |
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results_parsing_tests_asan_read_uhdm
Expired
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1.81 MB |
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results_parsing_tests_plugin_read_systemverilog
Expired
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1.53 MB |
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results_parsing_tests_plugin_read_uhdm
Expired
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1.78 MB |
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results_parsing_tests_release_read_systemverilog
Expired
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1.49 MB |
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results_parsing_tests_release_read_uhdm
Expired
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1.73 MB |
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tools
|
39.2 MB |
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top_artya7.bit
|
119 KB |
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