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Fix setting up scope for parameter simplification (#2674) #6063

Job	Run time
Build tools	10m 39s
Build Synlig Release	4m 54s
Emit Workflow Info	0s
Build Plugin	4m 26s
Build Synlig (ASAN)	8m 21s
Style check	1m 30s
Build Package	4m 57s
Verify README Correctness (Installation From Sources)	41m 0s
Build PySynlig	10m 32s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 27s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	16m 4s
Large Designs Tests / Black Parrot (ASIC synthesis)	41m 12s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	40m 33s
Large Designs Tests / Ibex (Vivado synthesis)	6m 27s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 23s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 6s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	33m 13s
Large Designs Tests / Opentitan parsing (quick)	5m 0s
Large Designs Tests / Opentitan (synthesis)	47m 42s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 28s
Parsing Tests / Test read_systemverilog release	4m 37s
Parsing Tests / Test read_uhdm release	4m 11s
Parsing Tests / Test read_systemverilog plugin	4m 35s
Parsing Tests / Test read_uhdm plugin	4m 19s
Parsing Tests / Test read_systemverilog asan	39m 37s
Parsing Tests / Test read_uhdm asan	25m 26s
Formal Verification Tests / simple	17m 16s
Formal Verification Tests / sv2v	16m 51s
Formal Verification Tests / yosys	14m 32s
Parsing Tests / Summary Generation	1m 34s
Parsing Tests / Generate AST diff	1m 58s
Release Package	11s
Verify README Correctness (Download And Run Release)	1m 54s
	7h 28m 55s

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