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Build(deps): Bump third_party/ibex from 87dfd07 to d2d55ed #6061

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Build(deps): Bump third_party/ibex from 87dfd07 to d2d55ed

Build(deps): Bump third_party/ibex from 87dfd07 to d2d55ed #6061

Triggered via pull request November 25, 2024 07:35
@dependabotdependabot[bot]
opened #2675
dependabot/submodules/third_party/ibex-d2d55ed
Status Failure
Total duration 1h 6m 40s
Artifacts 47

main.yml

on: pull_request
Matrix: build-binaries
Build tools
10m 41s
Build tools
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 42s
Style check
Verify README Correctness (Installation From Sources)
42m 27s
Verify README Correctness (Installation From Sources)
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests  /  Ibex (Vivado synthesis)
2m 44s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
5m 40s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
30m 59s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
57m 57s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
5m 23s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
15m 22s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
40m 40s
Large Designs Tests / Black Parrot (ASIC synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) with PySynlig)
39m 23s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
6m 33s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
1m 40s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 41s
Parsing Tests / Summary Generation
Release Package
0s
Release Package
Verify README Correctness (Download And Run Release)
0s
Verify README Correctness (Download And Run Release)
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Annotations

2 errors and 4 warnings
Large Designs Tests / Ibex (Vivado synthesis)
Process completed with exit code 2.
Large Designs Tests / Ibex (F4PGA synthesis)
Process completed with exit code 2.
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build third_party/OpenROAD-flow-scripts/logs third_party/OpenROAD-flow-scripts/reports third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
binaries-asan
291 MB
binaries-package
23.2 MB
binaries-plugin
41.7 MB
binaries-pysynlig
651 MB
binaries-release
41.9 MB
bp_e_bp_unicore_cfg.edif
3.92 MB
bsg-logs
5.56 MB
bsg-outputs
1.73 MB
formal-verification-logs-simple
18.8 MB
formal-verification-logs-sv2v
62.8 MB
formal-verification-logs-yosys
50.6 MB
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
616 KB
opentitan-logs-full
5.1 MB
opentitan-logs-quick
1.52 MB
plots_binaries-asan
54.6 KB
plots_binaries-package
31.2 KB
plots_binaries-plugin
28.8 KB
plots_binaries-pysynlig
57.7 KB
plots_binaries-release
28.4 KB
plots_blackparrot_synth_asic
244 KB
plots_blackparrot_synth_xilinx
101 KB
plots_blackparrot_synth_xilinx_python
231 KB
plots_build_tools
79.1 KB
plots_formal_verification_simple
110 KB
plots_formal_verification_sv2v
114 KB
plots_formal_verification_yosys
96.1 KB
plots_ibex_synth
18.9 KB
plots_ibex_synth_f4pga
43 KB
plots_opentitan_9d82960888_synth
176 KB
plots_opentitan_parse_report_full
99.6 KB
plots_opentitan_parse_report_quick
46.1 KB
plots_opentitan_synth
315 KB
plots_tests_asan_read_systemverilog
224 KB
plots_tests_asan_read_uhdm
168 KB
plots_tests_plugin_read_systemverilog
36 KB
plots_tests_plugin_read_uhdm
33.8 KB
plots_tests_release_read_systemverilog
36.1 KB
plots_tests_release_read_uhdm
33.1 KB
plots_veer_synth
37.8 KB
python_bp_e_bp_unicore_cfg.edif
3.92 MB
results_parsing_tests_asan_read_systemverilog Expired
1.6 MB
results_parsing_tests_asan_read_uhdm Expired
1.81 MB
results_parsing_tests_plugin_read_systemverilog Expired
1.53 MB
results_parsing_tests_plugin_read_uhdm Expired
1.78 MB
results_parsing_tests_release_read_systemverilog Expired
1.49 MB
results_parsing_tests_release_read_uhdm Expired
1.73 MB
tools
39.2 MB