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Fix setting up scope for parameter simplification #6060

Job	Run time
Build tools	10m 34s
Emit Workflow Info	0s
Build Synlig Release	4m 50s
Build Plugin	4m 24s
Style check	1m 31s
Build Synlig (ASAN)	8m 12s
Verify README Correctness (Installation From Sources)	42m 42s
Build Package	4m 48s
Build PySynlig	10m 37s
Large Designs Tests / Opentitan 9d82960888 (synthesis)	31m 29s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs	6m 27s
Large Designs Tests / Ibex (F4PGA synthesis)	11m 23s
Large Designs Tests / Ibex (Vivado synthesis)	6m 4s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)	16m 22s
Large Designs Tests / Opentitan parsing (full/top-down)	12m 19s
Large Designs Tests / VeeR-EH1 (synthesis)	5m 14s
Large Designs Tests / Opentitan (synthesis)	1h 6m 29s
Large Designs Tests / Opentitan parsing (quick)	5m 18s
Large Designs Tests / Black Parrot (ASIC synthesis)	40m 54s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)	40m 44s
Parsing Tests / Test read_systemverilog release	4m 24s
Parsing Tests / Test read_uhdm release	4m 7s
Parsing Tests / Test read_systemverilog plugin	4m 43s
Parsing Tests / Test read_uhdm plugin	4m 13s
Parsing Tests / Test read_systemverilog asan	35m 49s
Parsing Tests / Test read_uhdm asan	25m 32s
Formal Verification Tests / simple	17m 7s
Formal Verification Tests / sv2v	17m 15s
Formal Verification Tests / yosys	14m 37s
Parsing Tests / Summary Generation	1m 59s
Parsing Tests / Generate AST diff	1m 55s
Release Package	0s
Verify README Correctness (Download And Run Release)	0s
	7h 42m 2s

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