Build(deps): Bump third_party/black_parrot from 65c7db6 to 551f455
#6054
dependabot[bot]main.yml
on: pull_request
Matrix: build-binaries
Build tools
11m 23s
Emit Workflow Info
0s
Style check
1m 50s
Verify README Correctness (Installation From Sources)
42m 18s
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests
/
Ibex (Vivado synthesis)
6m 29s
Large Designs Tests
/
Ibex (F4PGA synthesis)
11m 51s
Large Designs Tests
/
Opentitan 9d82960888 (synthesis)
35m 4s
Large Designs Tests
/
Opentitan (synthesis)
51m 57s
Large Designs Tests
/
VeeR-EH1 (synthesis)
5m 44s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) FPGA synthesis)
3m 18s
Large Designs Tests
/
Black Parrot (ASIC synthesis)
3m 32s
Large Designs Tests
/
Black Parrot (AMD (Xilinx) with PySynlig)
4m 11s
Diff generated BSG Micro Designs tests
/
Parse and diff BSG Micro Designs
6m 34s
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests
/
Generate AST diff
2m 8s
Parsing Tests
/
Summary Generation
1m 39s
Verify README Correctness (Download And Run Release)
0s
Annotations
3 errors and 3 warnings
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Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Process completed with exit code 2.
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Large Designs Tests / Black Parrot (ASIC synthesis)
Process completed with exit code 2.
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Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Process completed with exit code 2.
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Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
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Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
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Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.
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Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
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binaries-asan
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292 MB |
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binaries-package
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23.1 MB |
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binaries-plugin
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41.6 MB |
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binaries-pysynlig
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652 MB |
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binaries-release
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41.8 MB |
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bsg-logs
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5.56 MB |
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bsg-outputs
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1.72 MB |
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formal-verification-logs-simple
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18.7 MB |
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formal-verification-logs-sv2v
|
62.6 MB |
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formal-verification-logs-yosys
|
50.8 MB |
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lowrisc_ibex_top_artya7_surelog_0.1.bit
|
105 KB |
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lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
|
616 KB |
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opentitan-logs-full
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5.09 MB |
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opentitan-logs-quick
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1.52 MB |
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plots_binaries-asan
|
54 KB |
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plots_binaries-package
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29.3 KB |
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plots_binaries-plugin
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30.8 KB |
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plots_binaries-pysynlig
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63.9 KB |
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plots_binaries-release
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31.6 KB |
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plots_blackparrot_synth_asic
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27.3 KB |
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plots_blackparrot_synth_xilinx
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26.8 KB |
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plots_blackparrot_synth_xilinx_python
|
30.7 KB |
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plots_build_tools
|
81.5 KB |
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plots_formal_verification_simple
|
112 KB |
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plots_formal_verification_sv2v
|
112 KB |
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plots_formal_verification_yosys
|
96.6 KB |
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plots_ibex_synth
|
46.1 KB |
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plots_ibex_synth_f4pga
|
82 KB |
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plots_opentitan_9d82960888_synth
|
197 KB |
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plots_opentitan_parse_report_full
|
85.8 KB |
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plots_opentitan_parse_report_quick
|
42.5 KB |
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plots_opentitan_synth
|
275 KB |
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plots_tests_asan_read_systemverilog
|
222 KB |
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plots_tests_asan_read_uhdm
|
169 KB |
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plots_tests_plugin_read_systemverilog
|
34.6 KB |
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plots_tests_plugin_read_uhdm
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35.5 KB |
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plots_tests_release_read_systemverilog
|
39.2 KB |
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plots_tests_release_read_uhdm
|
33.3 KB |
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plots_veer_synth
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39.3 KB |
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results_parsing_tests_asan_read_systemverilog
Expired
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1.6 MB |
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results_parsing_tests_asan_read_uhdm
Expired
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1.81 MB |
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results_parsing_tests_plugin_read_systemverilog
Expired
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1.53 MB |
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results_parsing_tests_plugin_read_uhdm
Expired
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1.78 MB |
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results_parsing_tests_release_read_systemverilog
Expired
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1.49 MB |
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results_parsing_tests_release_read_uhdm
Expired
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1.73 MB |
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tools
|
39.1 MB |
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top_artya7.bit
|
121 KB |
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