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@robertszczepanski I appreciate adding Veer cores, since they are Chips Alliance cores it's great to track them.
Veer-el2 supports Verilator as a simulator, however under sv-tests it fails due to a "##" unsupported error, perhaps because RV_ASSERT_ON is misset. Can you please fix that?
Also in the future as described in #1871, it would be much appreciated if all simulator results are audited before adding new tests to avoid failures such as these.
The text was updated successfully, but these errors were encountered:
@robertszczepanski I appreciate adding Veer cores, since they are Chips Alliance cores it's great to track them.
Veer-el2 supports Verilator as a simulator, however under sv-tests it fails due to a "##" unsupported error, perhaps because RV_ASSERT_ON is misset. Can you please fix that?
Also in the future as described in #1871, it would be much appreciated if all simulator results are audited before adding new tests to avoid failures such as these.
The text was updated successfully, but these errors were encountered: