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Merge pull request #26 from chipsalliance/dependabot/submodules/rvdec…
…oderdbtest/jvm/riscv-opcodes-6a1be96 Bump rvdecoderdbtest/jvm/riscv-opcodes from `feff9dc` to `6a1be96`
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Submodule riscv-opcodes
updated
12 files
+1 −0 | causes.csv | |
+15 −1 | encoding.h | |
+69 −15 | parse.py | |
+4 −0 | rv32_zicntr | |
+2 −0 | rv64_i | |
+7 −0 | rv_d | |
+15 −0 | rv_f | |
+29 −0 | rv_i | |
+7 −0 | rv_q | |
+5 −0 | rv_zfh | |
+5 −0 | rv_zicntr | |
+9 −17 | rv_zicsr |