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The new decoder #3534

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6 changes: 6 additions & 0 deletions .gitmodules
Original file line number Diff line number Diff line change
Expand Up @@ -7,3 +7,9 @@
[submodule "dependencies/chisel"]
path = dependencies/chisel
url = https://github.com/chipsalliance/chisel.git
[submodule "dependencies/rvdecoderdb"]
path = dependencies/rvdecoderdb
url = https://github.com/sequencer/rvdecoderdb.git
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After @jerryz123 approves, I will transfer this repo to chipsalliance.

[submodule "dependencies/riscv-opcodes"]
path = dependencies/riscv-opcodes
url = https://github.com/riscv/riscv-opcodes.git
22 changes: 22 additions & 0 deletions build.sc
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@ import coursier.maven.MavenRepository
import $file.dependencies.hardfloat.common
import $file.dependencies.cde.common
import $file.dependencies.chisel.build
import $file.dependencies.rvdecoderdb.common
import $file.common

object v {
Expand All @@ -16,6 +17,8 @@ object v {
"source" -> (ivy"org.chipsalliance::chisel:99", ivy"org.chipsalliance:::chisel-plugin:99"),
)
val mainargs = ivy"com.lihaoyi::mainargs:0.5.0"
val oslib = ivy"com.lihaoyi::os-lib:0.9.1"
val upickle = ivy"com.lihaoyi::upickle:3.1.3"
val json4sJackson = ivy"org.json4s::json4s-jackson:4.0.5"
val scalaReflect = ivy"org.scala-lang:scala-reflect:${scala}"
val sonatypesSnapshots = Seq(
Expand Down Expand Up @@ -79,6 +82,23 @@ trait CDE
override def millSourcePath = os.pwd / "dependencies" / "cde" / "cde"
}

object rvdecoderdb extends RVDecoderDB

trait RVDecoderDB
extends millbuild.dependencies.rvdecoderdb.common.RVDecoderDBJVMModule
with RocketChipPublishModule
with ScalaModule {

def scalaVersion: T[String] = T(v.scala)

def osLibIvy = v.oslib

def upickleIvy = v.upickle

override def millSourcePath = os.pwd / "dependencies" / "rvdecoderdb" / "rvdecoderdb"
}


object rocketchip extends Cross[RocketChip](v.chiselCrossVersions.keys.toSeq)

trait RocketChip
Expand All @@ -104,6 +124,8 @@ trait RocketChip

def cdeModule = cde

def rvdecoderdbModule = rvdecoderdb

def mainargsIvy = v.mainargs

def json4sJacksonIvy = v.json4sJackson
Expand Down
5 changes: 4 additions & 1 deletion common.sc
Original file line number Diff line number Diff line change
Expand Up @@ -45,11 +45,14 @@ trait RocketChipModule
// should be cde/common.sc#CDEModule
def cdeModule: ScalaModule

// should be dependencies/rvdecoderdb/common.sc#RVDecoderDB
def rvdecoderdbModule: ScalaModule

def mainargsIvy: Dep

def json4sJacksonIvy: Dep

override def moduleDeps = super.moduleDeps ++ Seq(macrosModule, hardfloatModule, cdeModule)
override def moduleDeps = super.moduleDeps ++ Seq(macrosModule, hardfloatModule, cdeModule, rvdecoderdbModule)

override def ivyDeps = T(
super.ivyDeps() ++ Agg(
Expand Down
1 change: 1 addition & 0 deletions dependencies/riscv-opcodes
Submodule riscv-opcodes added at 2c457d
1 change: 1 addition & 0 deletions dependencies/rvdecoderdb
Submodule rvdecoderdb added at 2b322c
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@
package freechips.rocketchip.rocket

import chisel3.util._
import freechips.rocketchip.rocket._

object CustomInstructions {
def MNRET = BitPat("b01110000001000000000000001110011")
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@ package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.BitPat
import chisel3.util.experimental.decode._
import freechips.rocketchip.rocket._

object DecodeLogic
{
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@ import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
import freechips.rocketchip.rocket._
import Instructions._
import CustomInstructions._

Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@
package freechips.rocketchip.rocket

import chisel3.util._
import freechips.rocketchip.rocket._

/* make EXTENSIONS="rv_* rv64*" inst.chisel */

Expand Down
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