remove master/slave from remaining modules

src/main/scala/diplomacy/Parameters.scala

@@ -15,7 +15,7 @@ object RegionType {
   }
 
   case object CACHED      extends T // an intermediate agent may have cached a copy of the region for you
-  case object TRACKED     extends T // the region may have been cached by another master, but coherence is being provided
+  case object TRACKED     extends T // the region may have been cached by another client, but coherence is being provided
   case object UNCACHED    extends T // the region has not been cached yet, but should be cached when possible
   case object IDEMPOTENT  extends T // gets return most recently put content, but content should not be cached
   case object VOLATILE    extends T // content may change without a put, but puts and gets have no side effects
@@ -119,7 +119,7 @@ object TransferSizes {
   def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
   def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
 
-  implicit def asBool(x: TransferSizes) = !x.none
+  implicit def asBool(x: TransferSizes): Boolean = !x.none
 }
 
 // AddressSets specify the address space managed by the manager

src/main/scala/formal/FormalUtils.scala

@@ -12,10 +12,10 @@ sealed abstract class MonitorDirection(name: String) {
   def flip: MonitorDirection
 }
 object MonitorDirection {
-  // Also known as master, effectively contains assumes
+  // Also known as client, effectively contains assumes
   object Driver  extends MonitorDirection("Driver") { override def flip: MonitorDirection = Receiver }
 
-  // Also known as slave, effectively contains asserts
+  // Also known as manager, effectively contains asserts
   object Receiver extends MonitorDirection("Receiver") { override def flip: MonitorDirection = Driver }
 
   object Monitor extends MonitorDirection("Monitor") { override def flip: MonitorDirection = Monitor }

src/main/scala/groundtest/Configs.scala

@@ -6,10 +6,10 @@ package freechips.rocketchip.groundtest
 import org.chipsalliance.cde.config._
 
 import freechips.rocketchip.devices.tilelink.{CLINTKey, PLICKey}
-import freechips.rocketchip.devices.debug.{DebugModuleKey}
+import freechips.rocketchip.devices.debug.DebugModuleKey
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system.BaseConfig
-import freechips.rocketchip.rocket.{DCacheParams}
+import freechips.rocketchip.rocket.DCacheParams
 
 /** Actual testing target Configs */
 
@@ -44,7 +44,7 @@ class WithTraceGen(
   case TilesLocated(InSubsystem) => {
     val prev = up(TilesLocated(InSubsystem), site)
     val idOffset = up(NumTiles)
-    val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
+    val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.client.base)).getOrElse(0x0L)
     params.zipWithIndex.map { case (dcp, i) =>
       TraceGenTileAttachParams(
         tileParams = TraceGenParams(

src/main/scala/groundtest/GroundTestSubsystem.scala

@@ -23,7 +23,7 @@ class GroundTestSubsystem(implicit p: Parameters)
   with HasHierarchicalElements
   with HasTileNotificationSinks
   with HasTileInputConstants
-  with CanHaveMasterAXI4MemPort
+  with CanHaveManagerAXI4MemPort
 {
   val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), beatBytes=tlBusWrapperLocationMap.get(PBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).beatBytes))
   tlBusWrapperLocationMap.lift(PBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).coupleTo("TestRAM") { testram.node := TLFragmenter(tlBusWrapperLocationMap.lift(PBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))))) := _ }

src/main/scala/groundtest/Tile.scala

@@ -40,7 +40,7 @@ abstract class GroundTestTile(
 {
   val cpuDevice: SimpleDevice = new SimpleDevice("groundtest", Nil)
   val intOutwardNode = None
-  val slaveNode: TLInwardNode = TLIdentityNode()
+  val managerNode: TLInwardNode = TLIdentityNode()
   val statusNode = BundleBridgeSource(() => new GroundTestStatus)
 
   val dcacheOpt = params.dcache.map { dc => LazyModule(p(BuildHellaCache)(this)(p)) }

src/main/scala/groundtest/TraceGen.scala

@@ -622,7 +622,7 @@ class TraceGenTile private(
   def this(params: TraceGenParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
     this(params, crossing.crossingType, lookup, p)
 
-  val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcacheOpt.map(_.node).getOrElse(TLTempNode())
+  val clientNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcacheOpt.map(_.node).getOrElse(TLTempNode())
 
   override lazy val module = new TraceGenTileModuleImp(this)
 }

src/main/scala/jtag/JtagTap.scala

@@ -7,7 +7,7 @@ import scala.collection.SortedMap
 import chisel3._
 import org.chipsalliance.cde.config.Parameters
 
-/** JTAG signals, viewed from the master side
+/** JTAG signals, viewed from the driver side
   */
 class JTAGIO(hasTRSTn: Boolean = false) extends Bundle {
   val TRSTn = if (hasTRSTn) Some(Output(Bool())) else None

src/main/scala/jtag/JtagUtils.scala

@@ -21,7 +21,7 @@ object JtagIdcode {
     BigInt(version) << 28 | BigInt(partNumber) << 12 | BigInt(mfrId) << 1 | 1
   }
 
-  /** A dummy manufacturer ID, not to be used per 12.2.1b since bus masters may shift this out to
+  /** A dummy manufacturer ID, not to be used per 12.2.1b since bus drivers may shift this out to
     * determine the end of a bus.
     */
   def dummyMfrId: Int = 0x7f