Fix VCS VILIOP errors

Signed-off-by: Krzysztof Boronski <[email protected]>

src/i3c_wrapper.sv

@@ -102,8 +102,8 @@ module i3c_wrapper #(
     output logic sel_od_pp_o
 `else
     // I3C bus IO
-    inout  logic i3c_scl_io,
-    inout  logic i3c_sda_io
+    inout  wire i3c_scl_io,
+    inout  wire i3c_sda_io
 `endif
 
     // TODO: Add interrupts

src/phy/buf_od.sv

@@ -11,7 +11,7 @@
 */
 module buf_od (
     input logic drive_low,
-    inout logic buf_od_o
+    inout wire  buf_od_o
 );
 
   assign buf_od_o = drive_low ? 1'b0 : 1'bz;

src/phy/bufs.sv

@@ -14,7 +14,7 @@
 module bufs (
     input logic phy_data_i,
     input logic sel_od_pp_i,
-    inout logic phy_data_io
+    inout wire  phy_data_io
 );
 
   logic phy_data_i_z;

src/phy/i3c_io.sv

@@ -24,8 +24,8 @@ module i3c_io (
     input logic sel_od_pp_i,
 
     // Bus {SCL, SDA}
-    inout logic scl_io,
-    inout logic sda_io
+    inout wire scl_io,
+    inout wire sda_io
 );
 
   wire scl_io_int;