Remove duplicated usage of Verilog files from Caliptra in Makefiles

chipsalliance · Dec 18, 2024 · c0b9612 · c0b9612
1 parent dbd9fa4
commit c0b9612
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Showing 5 changed files with 18 additions and 13 deletions.
diff --git a/verification/cocotb/block/hci_queues_ahb/Makefile b/verification/cocotb/block/hci_queues_ahb/Makefile
@@ -15,8 +15,9 @@ TOPLEVEL     = hci_queues_wrapper
 # Set appropriate bus interface via Cocotb's PLUSARGS:
 override PLUSARGS := $(strip +FrontendBusInterface=AHB $(PLUSARGS))
 
-VERILOG_SOURCES  = \
-    $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv \
+include $(TEST_DIR)/../../caliptra_common.mk
+
+VERILOG_SOURCES += \
     $(CALIPTRA_ROOT)/src/libs/rtl/ahb_defines_pkg.sv \
     $(SRC_DIR)/i3c_pkg.sv \
     $(SRC_DIR)/csr/I3CCSR_pkg.sv \

diff --git a/verification/cocotb/block/hci_queues_axi/Makefile b/verification/cocotb/block/hci_queues_axi/Makefile
@@ -15,8 +15,9 @@ TOPLEVEL     = hci_queues_wrapper
 # Set appropriate bus interface via Cocotb's PLUSARGS:
 override PLUSARGS := $(strip +FrontendBusInterface=AXI $(PLUSARGS))
 
-VERILOG_SOURCES  = \
-    $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv \
+include $(TEST_DIR)/../../caliptra_common.mk
+
+VERILOG_SOURCES += \
     $(SRC_DIR)/i3c_pkg.sv \
     $(SRC_DIR)/csr/I3CCSR_pkg.sv \
     $(SRC_DIR)/csr/I3CCSR.sv \

diff --git a/verification/cocotb/block/i3c_phy_io/Makefile b/verification/cocotb/block/i3c_phy_io/Makefile
@@ -13,7 +13,9 @@ TEST_FILES   = $(sort $(wildcard test_*.py))
 MODULE      ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES)))
 TOPLEVEL     = i3c_phy_io_wrapper
 
-VERILOG_SOURCES  = \
+include $(TEST_DIR)/../../caliptra_common.mk
+
+VERILOG_SOURCES += \
 	$(SRC_DIR)/phy/buf_od.sv \
 	$(SRC_DIR)/phy/buf_pp.sv \
 	$(SRC_DIR)/phy/bufs.sv \

diff --git a/verification/cocotb/caliptra_common.mk b/verification/cocotb/caliptra_common.mk
@@ -0,0 +1,9 @@
+CALIPTRA_SOURCES = \
+	$(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_pkg.sv \
+	$(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv \
+	$(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_assert.sv \
+	$(CALIPTRA_ROOT)/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv \
+	$(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_flop.sv \
+	$(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
+
+VERILOG_SOURCES += $(CALIPTRA_SOURCES)
diff --git a/verification/cocotb/common.mk b/verification/cocotb/common.mk
@@ -14,14 +14,6 @@ $(info From common.mk, CURDIR is $(CURDIR))
 # Set pythonpath so that tests can access common modules
 export PYTHONPATH := $(PYTHONPATH):$(CURDIR)/common
 
-# Common sources
-COMMON_SOURCES  = \
-    $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_pkg.sv \
-    $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_assert.sv \
-    $(CALIPTRA_ROOT)/src/caliptra_prim_generic/rtl/caliptra_prim_generic_flop.sv \
-    $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_flop.sv \
-    $(CALIPTRA_ROOT)/src/caliptra_prim/rtl/caliptra_prim_flop_2sync.sv
-
 VERILOG_INCLUDE_DIRS= \
     $(CALIPTRA_ROOT)/src/libs/rtl \
     $(CALIPTRA_ROOT)/src/caliptra_prim/rtl \